1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 // A2 Processor User's Manual.
12 // IBM (as updated in) 2010.
14 //===----------------------------------------------------------------------===//
15 // Functional units on the PowerPC A2 chip sets
17 def A2_XU : FuncUnit; // A2_XU pipeline
18 def A2_FU : FuncUnit; // FI pipeline
21 // This file defines the itinerary class data for the PPC A2 processor.
23 //===----------------------------------------------------------------------===//
26 def PPCA2Itineraries : ProcessorItineraries<
28 InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>],
30 InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>],
32 InstrItinData<IIC_IntISEL, [InstrStage<1, [A2_XU]>],
34 InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>],
36 InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>],
38 InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>],
40 InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>],
42 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>],
44 InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>],
46 InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>],
48 InstrItinData<IIC_IntRotateD, [InstrStage<1, [A2_XU]>],
50 InstrItinData<IIC_IntRotateDI, [InstrStage<1, [A2_XU]>],
52 InstrItinData<IIC_IntShift, [InstrStage<1, [A2_XU]>],
54 InstrItinData<IIC_IntTrapW, [InstrStage<1, [A2_XU]>],
56 InstrItinData<IIC_IntTrapD, [InstrStage<1, [A2_XU]>],
58 InstrItinData<IIC_BrB, [InstrStage<1, [A2_XU]>],
60 InstrItinData<IIC_BrCR, [InstrStage<1, [A2_XU]>],
62 InstrItinData<IIC_BrMCR, [InstrStage<1, [A2_XU]>],
64 InstrItinData<IIC_BrMCRX, [InstrStage<1, [A2_XU]>],
66 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [A2_XU]>],
68 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [A2_XU]>],
70 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [A2_XU]>],
72 InstrItinData<IIC_LdStLoad, [InstrStage<1, [A2_XU]>],
74 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>],
76 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [A2_XU]>],
78 InstrItinData<IIC_LdStLDU, [InstrStage<1, [A2_XU]>],
80 InstrItinData<IIC_LdStLDUX, [InstrStage<1, [A2_XU]>],
82 InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>],
84 InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [A2_XU]>],
86 InstrItinData<IIC_LdStICBI, [InstrStage<1, [A2_XU]>],
88 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [A2_XU]>],
90 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [A2_XU]>],
92 InstrItinData<IIC_LdStLFD, [InstrStage<1, [A2_XU]>],
94 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [A2_XU]>],
96 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [A2_XU]>],
98 InstrItinData<IIC_LdStLHA, [InstrStage<1, [A2_XU]>],
100 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [A2_XU]>],
102 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [A2_XU]>],
104 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>],
105 [82, 0, 0]>, // L2 latency
106 InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>],
108 InstrItinData<IIC_LdStSTDU, [InstrStage<1, [A2_XU]>],
110 InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [A2_XU]>],
112 InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>],
113 [82, 0, 0]>, // L2 latency
114 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>],
115 [82, 0, 0]>, // L2 latency
116 InstrItinData<IIC_LdStSync, [InstrStage<1, [A2_XU]>],
118 InstrItinData<IIC_SprISYNC, [InstrStage<1, [A2_XU]>],
120 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [A2_XU]>],
122 InstrItinData<IIC_SprMFCR, [InstrStage<1, [A2_XU]>],
124 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [A2_XU]>],
126 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [A2_XU]>],
128 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [A2_XU]>],
130 InstrItinData<IIC_SprMFTB, [InstrStage<1, [A2_XU]>],
132 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [A2_XU]>],
134 InstrItinData<IIC_SprRFI, [InstrStage<1, [A2_XU]>],
136 InstrItinData<IIC_SprSC, [InstrStage<1, [A2_XU]>],
138 InstrItinData<IIC_FPGeneral, [InstrStage<1, [A2_FU]>],
140 InstrItinData<IIC_FPAddSub, [InstrStage<1, [A2_FU]>],
142 InstrItinData<IIC_FPCompare, [InstrStage<1, [A2_FU]>],
144 InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>],
146 InstrItinData<IIC_FPDivS, [InstrStage<1, [A2_FU]>],
148 InstrItinData<IIC_FPSqrtD, [InstrStage<1, [A2_FU]>],
150 InstrItinData<IIC_FPSqrtS, [InstrStage<1, [A2_FU]>],
152 InstrItinData<IIC_FPFused, [InstrStage<1, [A2_FU]>],
154 InstrItinData<IIC_FPRes, [InstrStage<1, [A2_FU]>],
158 // ===---------------------------------------------------------------------===//
159 // A2 machine model for scheduling and other instruction cost heuristics.
161 def PPCA2Model : SchedMachineModel {
162 let IssueWidth = 1; // 1 instruction is dispatched per cycle.
163 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
164 let LoadLatency = 6; // Optimistic load latency assuming bypass.
165 // This is overriden by OperandCycles if the
166 // Itineraries are queried instead.
167 let MispredictPenalty = 13;
169 let Itineraries = PPCA2Itineraries;