lib/Target/PowerPC/PPCScheduleA2.td

   1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 // Primary reference:
  11 // A2 Processor User's Manual.
  12 // IBM (as updated in) 2010.
  13
  14 //===----------------------------------------------------------------------===//
  15 // Functional units on the PowerPC A2 chip sets
  16 //
  17 def IU0to3_0  : FuncUnit; // Fetch unit 1 to 4 slot 1
  18 def IU0to3_1  : FuncUnit; // Fetch unit 1 to 4 slot 2
  19 def IU0to3_2  : FuncUnit; // Fetch unit 1 to 4 slot 3
  20 def IU0to3_3  : FuncUnit; // Fetch unit 1 to 4 slot 4
  21 def IU4_0  : FuncUnit; // Instruction buffer slot 1
  22 def IU4_1  : FuncUnit; // Instruction buffer slot 2
  23 def IU4_2  : FuncUnit; // Instruction buffer slot 3
  24 def IU4_3  : FuncUnit; // Instruction buffer slot 4
  25 def IU4_4  : FuncUnit; // Instruction buffer slot 5
  26 def IU4_5  : FuncUnit; // Instruction buffer slot 6
  27 def IU4_6  : FuncUnit; // Instruction buffer slot 7
  28 def IU4_7  : FuncUnit; // Instruction buffer slot 8
  29 def IU5    : FuncUnit; // Dependency resolution
  30 def IU6    : FuncUnit; // Instruction issue
  31 def RF0    : FuncUnit;
  32 def XRF1   : FuncUnit;
  33 def XEX1   : FuncUnit; // Execution stage 1 for the XU pipeline
  34 def XEX2   : FuncUnit; // Execution stage 2 for the XU pipeline
  35 def XEX3   : FuncUnit; // Execution stage 3 for the XU pipeline
  36 def XEX4   : FuncUnit; // Execution stage 4 for the XU pipeline
  37 def XEX5   : FuncUnit; // Execution stage 5 for the XU pipeline
  38 def XEX6   : FuncUnit; // Execution stage 6 for the XU pipeline
  39 def FRF1   : FuncUnit;
  40 def FEX1   : FuncUnit; // Execution stage 1 for the FU pipeline
  41 def FEX2   : FuncUnit; // Execution stage 2 for the FU pipeline
  42 def FEX3   : FuncUnit; // Execution stage 3 for the FU pipeline
  43 def FEX4   : FuncUnit; // Execution stage 4 for the FU pipeline
  44 def FEX5   : FuncUnit; // Execution stage 5 for the FU pipeline
  45 def FEX6   : FuncUnit; // Execution stage 6 for the FU pipeline
  46
  47 def CR_Bypass  : Bypass; // The bypass for condition regs.
  48 //def GPR_Bypass : Bypass; // The bypass for general-purpose regs.
  49 //def FPR_Bypass : Bypass; // The bypass for floating-point regs.
  50
  51 //
  52 // This file defines the itinerary class data for the PPC A2 processor.
  53 //
  54 //===----------------------------------------------------------------------===//
  55
  56
  57 def PPCA2Itineraries : ProcessorItineraries<
  58   [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3,
  59    IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7,
  60    IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6,
  61    FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6],
  62   [CR_Bypass, GPR_Bypass, FPR_Bypass], [
  63   InstrItinData<IntGeneral  , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
  64                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
  65                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
  66                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
  67                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
  68                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
  69                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
  70                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
  71                               [10, 7, 7],
  72                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
  73   InstrItinData<IntCompare  , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
  74                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
  75                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
  76                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
  77                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
  78                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
  79                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
  80                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
  81                               [10, 7, 7],
  82                               [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
  83   InstrItinData<IntDivW     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
  84                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
  85                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
  86                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
  87                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
  88                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
  89                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
  90                                InstrStage<1, [XEX5]>, InstrStage<38, [XEX6]>],
  91                               [53, 7, 7],
  92                               [NoBypass, GPR_Bypass, GPR_Bypass]>,
  93   InstrItinData<IntMFFS     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
  94                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
  95                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
  96                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
  97                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
  98                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
  99                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 100                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 101                               [10, 7, 7],
 102                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 103   InstrItinData<IntMTFSB0   , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 104                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 105                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 106                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 107                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 108                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 109                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 110                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 111                               [10, 7, 7],
 112                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 113   InstrItinData<IntMulHW    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 114                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 115                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 116                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 117                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 118                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 119                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 120                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 121                               [14, 7, 7],
 122                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 123   InstrItinData<IntMulHWU   , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 124                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 125                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 126                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 127                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 128                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 129                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 130                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 131                               [14, 7, 7],
 132                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 133   InstrItinData<IntMulLI    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 134                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 135                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 136                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 137                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 138                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 139                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 140                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 141                               [15, 7, 7],
 142                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 143   InstrItinData<IntRotate   , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 144                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 145                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 146                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 147                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 148                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 149                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 150                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 151                               [10, 7, 7],
 152                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 153   InstrItinData<IntShift    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 154                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 155                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 156                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 157                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 158                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 159                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 160                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 161                               [10, 7, 7],
 162                               [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 163   InstrItinData<IntTrapW    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 164                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 165                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 166                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 167                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 168                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 169                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 170                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 171                               [10, 7, 7],
 172                               [GPR_Bypass, GPR_Bypass]>,
 173   InstrItinData<BrB         , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 174                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 175                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 176                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 177                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 178                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 179                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 180                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 181                               [15, 7, 7],
 182                               [NoBypass, GPR_Bypass]>,
 183   InstrItinData<BrCR        , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 184                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 185                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 186                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 187                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 188                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 189                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 190                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 191                               [10, 7, 7],
 192                               [CR_Bypass, CR_Bypass, CR_Bypass]>,
 193   InstrItinData<BrMCR       , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 194                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 195                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 196                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 197                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 198                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 199                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 200                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 201                               [10, 7, 7],
 202                               [CR_Bypass, CR_Bypass, CR_Bypass]>,
 203   InstrItinData<BrMCRX      , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 204                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 205                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 206                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 207                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 208                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 209                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 210                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 211                               [10, 7, 7],
 212                               [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
 213   InstrItinData<LdStDCBA    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 214                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 215                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 216                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 217                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 218                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 219                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 220                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 221                               [13, 11],
 222                               [NoBypass, GPR_Bypass]>,
 223   InstrItinData<LdStDCBF    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 224                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 225                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 226                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 227                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 228                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 229                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 230                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 231                               [13, 11],
 232                               [NoBypass, GPR_Bypass]>,
 233   InstrItinData<LdStDCBI    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 234                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 235                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 236                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 237                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 238                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 239                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 240                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 241                               [13, 11],
 242                               [NoBypass, GPR_Bypass]>,
 243   InstrItinData<LdStLoad    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 244                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 245                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 246                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 247                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 248                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 249                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 250                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 251                               [14, 7],
 252                               [GPR_Bypass, GPR_Bypass]>,
 253   InstrItinData<LdStStore   , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 254                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 255                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 256                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 257                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 258                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 259                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 260                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 261                               [13, 7],
 262                               [GPR_Bypass, GPR_Bypass]>,
 263   InstrItinData<LdStICBI    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 264                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 265                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 266                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 267                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 268                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 269                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 270                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 271                               [14, 7],
 272                               [NoBypass, GPR_Bypass]>,
 273   InstrItinData<LdStUX      , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 274                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 275                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 276                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 277                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 278                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 279                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 280                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 281                               [14, 7, 7],
 282                               [NoBypass, FPR_Bypass, FPR_Bypass]>,
 283   InstrItinData<LdStLFD     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 284                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 285                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 286                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 287                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 288                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 289                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 290                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 291                               [14, 7, 7],
 292                               [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 293   InstrItinData<LdStLFDU    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 294                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 295                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 296                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 297                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 298                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 299                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 300                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 301                               [14, 7, 7],
 302                               [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
 303   InstrItinData<LdStLHA     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 304                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 305                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 306                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 307                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 308                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 309                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 310                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 311                               [14, 7],
 312                               [NoBypass, GPR_Bypass]>,
 313   InstrItinData<LdStLMW     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 314                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 315                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 316                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 317                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 318                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 319                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 320                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 321                               [14, 7],
 322                               [NoBypass, GPR_Bypass]>,
 323   InstrItinData<LdStLWARX   , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 324                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 325                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 326                                InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
 327                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 328                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 329                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 330                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 331                               [26, 7],
 332                               [NoBypass, GPR_Bypass]>,
 333   InstrItinData<LdStSTD     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 334                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 335                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 336                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 337                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 338                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 339                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 340                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 341                               [13, 7],
 342                               [GPR_Bypass, GPR_Bypass]>,
 343   InstrItinData<LdStSTDCX   , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 344                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 345                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 346                                InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
 347                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 348                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 349                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 350                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 351                               [26, 7],
 352                               [NoBypass, GPR_Bypass]>,
 353   InstrItinData<LdStSTWCX   , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 354                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 355                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 356                                InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
 357                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 358                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 359                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 360                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 361                               [26, 7],
 362                               [NoBypass, GPR_Bypass]>,
 363   InstrItinData<LdStSync    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 364                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 365                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 366                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 367                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 368                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 369                                InstrStage<1, [XEX3]>, InstrStage<12, [XEX4]>,
 370                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>]>,
 371   InstrItinData<SprISYNC    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 372                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 373                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 374                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 375                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 376                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 377                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 378                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
 379   InstrItinData<SprMFSR     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 380                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 381                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 382                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 383                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 384                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 385                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 386                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 387                               [15, 7],
 388                               [GPR_Bypass, NoBypass]>,
 389   InstrItinData<SprMTMSR    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 390                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 391                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 392                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 393                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 394                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 395                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 396                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 397                               [15, 7],
 398                               [NoBypass, GPR_Bypass]>,
 399   InstrItinData<SprMTSR     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 400                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 401                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 402                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 403                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 404                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 405                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 406                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 407                               [15, 7],
 408                               [NoBypass, GPR_Bypass]>,
 409   InstrItinData<SprTLBSYNC  , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 410                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 411                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 412                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 413                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 414                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 415                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 416                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
 417   InstrItinData<SprMFCR     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 418                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 419                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 420                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 421                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 422                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 423                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 424                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 425                               [10, 7],
 426                               [GPR_Bypass, CR_Bypass]>,
 427   InstrItinData<SprMFMSR    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 428                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 429                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 430                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 431                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 432                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 433                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 434                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 435                               [15, 7],
 436                               [GPR_Bypass, NoBypass]>,
 437   InstrItinData<SprMFSPR    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 438                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 439                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 440                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 441                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 442                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 443                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 444                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 445                               [15, 7],
 446                               [NoBypass, GPR_Bypass]>,
 447   InstrItinData<SprMFTB     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 448                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 449                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 450                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 451                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 452                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 453                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 454                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
 455                               [29, 7],
 456                               [NoBypass, GPR_Bypass]>,
 457   InstrItinData<SprMTSPR    , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 458                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 459                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 460                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 461                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 462                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 463                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 464                                InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
 465                               [15, 7],
 466                               [NoBypass, GPR_Bypass]>,
 467   InstrItinData<SprMTSRIN   , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 468                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 469                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 470                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 471                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 472                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 473                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 474                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
 475                               [29, 7],
 476                               [NoBypass, GPR_Bypass]>,
 477   InstrItinData<SprRFI      , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 478                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 479                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 480                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 481                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 482                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 483                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 484                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
 485                               [29, 7],
 486                               [NoBypass, GPR_Bypass]>,
 487   InstrItinData<SprSC       , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 488                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 489                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 490                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 491                                InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
 492                                InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
 493                                InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
 494                                InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
 495                               [29, 7],
 496                               [NoBypass, GPR_Bypass]>,
 497   InstrItinData<FPGeneral   , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 498                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 499                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 500                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 501                                InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
 502                                InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
 503                                InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
 504                                InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
 505                               [15, 7, 7],
 506                               [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 507   InstrItinData<FPCompare   , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 508                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 509                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 510                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 511                                InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
 512                                InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
 513                                InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
 514                                InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
 515                               [13, 7, 7],
 516                               [CR_Bypass, FPR_Bypass, FPR_Bypass]>,
 517   InstrItinData<FPDivD      , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 518                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 519                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 520                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 521                                InstrStage<1, [RF0]>, InstrStage<71, [FRF1], 0>,
 522                                InstrStage<71, [FEX1], 0>, InstrStage<71, [FEX2], 0>,
 523                                InstrStage<71, [FEX3], 0>, InstrStage<71, [FEX4], 0>,
 524                                InstrStage<71, [FEX5], 0>, InstrStage<71, [FEX6]>],
 525                               [86, 7, 7],
 526                               [NoBypass, FPR_Bypass, FPR_Bypass]>,
 527   InstrItinData<FPDivS      , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 528                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 529                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 530                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 531                                InstrStage<1, [RF0]>, InstrStage<58, [FRF1], 0>,
 532                                InstrStage<58, [FEX1], 0>, InstrStage<58, [FEX2], 0>,
 533                                InstrStage<58, [FEX3], 0>, InstrStage<58, [FEX4], 0>,
 534                                InstrStage<58, [FEX5], 0>, InstrStage<58, [FEX6]>],
 535                               [73, 7, 7],
 536                               [NoBypass, FPR_Bypass, FPR_Bypass]>,
 537   InstrItinData<FPSqrt      , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 538                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 539                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 540                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 541                                InstrStage<1, [RF0]>, InstrStage<68, [FRF1], 0>,
 542                                InstrStage<68, [FEX1], 0>, InstrStage<68, [FEX2], 0>,
 543                                InstrStage<68, [FEX3], 0>, InstrStage<68, [FEX4], 0>,
 544                                InstrStage<68, [FEX5], 0>, InstrStage<68, [FEX6]>],
 545                               [86, 7], // FIXME: should be [86, 7] for double
 546                                        // and [82, 7] for single. Likewise,
 547                                        // the FEX? cycle count should be 68
 548                                        // for double and 64 for single.
 549                               [NoBypass, FPR_Bypass]>,
 550   InstrItinData<FPFused     , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 551                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 552                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 553                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 554                                InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
 555                                InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
 556                                InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
 557                                InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
 558                               [15, 7, 7, 7],
 559                               [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
 560   InstrItinData<FPRes       , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
 561                                InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
 562                                               IU4_4, IU4_5, IU4_6, IU4_7]>,
 563                                InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
 564                                InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
 565                                InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
 566                                InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
 567                                InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
 568                               [15, 7],
 569                               [FPR_Bypass, FPR_Bypass]>
 570 ]>;