lib/Target/PowerPC/PPCScheduleA2.td

   1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 // Primary reference:
  11 // A2 Processor User's Manual.
  12 // IBM (as updated in) 2010.
  13
  14 //===----------------------------------------------------------------------===//
  15 // Functional units on the PowerPC A2 chip sets
  16 //
  17 def XU     : FuncUnit; // XU pipeline
  18 def FU     : FuncUnit; // FI pipeline
  19
  20 //
  21 // This file defines the itinerary class data for the PPC A2 processor.
  22 //
  23 //===----------------------------------------------------------------------===//
  24
  25
  26 def PPCA2Itineraries : ProcessorItineraries<
  27   [XU, FU], [], [
  28   InstrItinData<IIC_IntSimple,   [InstrStage<1, [XU]>],
  29                                  [1, 1, 1]>,
  30   InstrItinData<IIC_IntGeneral,  [InstrStage<1, [XU]>],
  31                                  [2, 1, 1]>,
  32   InstrItinData<IIC_IntCompare,  [InstrStage<1, [XU]>],
  33                                  [2, 1, 1]>,
  34   InstrItinData<IIC_IntDivW,     [InstrStage<1, [XU]>],
  35                                  [39, 1, 1]>,
  36   InstrItinData<IIC_IntDivD,     [InstrStage<1, [XU]>],
  37                                  [71, 1, 1]>,
  38   InstrItinData<IIC_IntMulHW,    [InstrStage<1, [XU]>],
  39                                  [5, 1, 1]>,
  40   InstrItinData<IIC_IntMulHWU,   [InstrStage<1, [XU]>],
  41                                  [5, 1, 1]>,
  42   InstrItinData<IIC_IntMulLI,    [InstrStage<1, [XU]>],
  43                                  [6, 1, 1]>,
  44   InstrItinData<IIC_IntRotate,   [InstrStage<1, [XU]>],
  45                                  [2, 1, 1]>,
  46   InstrItinData<IIC_IntRotateD,  [InstrStage<1, [XU]>],
  47                                  [2, 1, 1]>,
  48   InstrItinData<IIC_IntRotateDI, [InstrStage<1, [XU]>],
  49                                  [2, 1, 1]>,
  50   InstrItinData<IIC_IntShift,    [InstrStage<1, [XU]>],
  51                                  [2, 1, 1]>,
  52   InstrItinData<IIC_IntTrapW,    [InstrStage<1, [XU]>],
  53                                  [2, 1]>,
  54   InstrItinData<IIC_IntTrapD,    [InstrStage<1, [XU]>],
  55                                  [2, 1]>,
  56   InstrItinData<IIC_BrB,         [InstrStage<1, [XU]>],
  57                                  [6, 1, 1]>,
  58   InstrItinData<IIC_BrCR,        [InstrStage<1, [XU]>],
  59                                  [1, 1, 1]>,
  60   InstrItinData<IIC_BrMCR,       [InstrStage<1, [XU]>],
  61                                  [5, 1, 1]>,
  62   InstrItinData<IIC_BrMCRX,      [InstrStage<1, [XU]>],
  63                                  [1, 1, 1]>,
  64   InstrItinData<IIC_LdStDCBA,    [InstrStage<1, [XU]>],
  65                                  [1, 1, 1]>,
  66   InstrItinData<IIC_LdStDCBF,    [InstrStage<1, [XU]>],
  67                                  [1, 1, 1]>,
  68   InstrItinData<IIC_LdStDCBI,    [InstrStage<1, [XU]>],
  69                                  [1, 1, 1]>,
  70   InstrItinData<IIC_LdStLoad,    [InstrStage<1, [XU]>],
  71                                  [6, 1, 1]>,
  72   InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [XU]>],
  73                                  [6, 8, 1, 1]>,
  74   InstrItinData<IIC_LdStLDU,     [InstrStage<1, [XU]>],
  75                                  [6, 1, 1]>,
  76   InstrItinData<IIC_LdStStore,   [InstrStage<1, [XU]>],
  77                                  [1, 1, 1]>,
  78   InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [XU]>],
  79                                  [2, 1, 1, 1]>,
  80   InstrItinData<IIC_LdStICBI,    [InstrStage<1, [XU]>],
  81                                  [16, 1, 1]>,
  82   InstrItinData<IIC_LdStSTFD,    [InstrStage<1, [XU]>],
  83                                  [1, 1, 1]>,
  84   InstrItinData<IIC_LdStSTFDU,   [InstrStage<1, [XU]>],
  85                                  [2, 1, 1, 1]>,
  86   InstrItinData<IIC_LdStLFD,     [InstrStage<1, [XU]>],
  87                                  [7, 1, 1]>,
  88   InstrItinData<IIC_LdStLFDU,    [InstrStage<1, [XU]>],
  89                                  [7, 9, 1, 1]>,
  90   InstrItinData<IIC_LdStLHA,     [InstrStage<1, [XU]>],
  91                                  [6, 1, 1]>,
  92   InstrItinData<IIC_LdStLHAU,    [InstrStage<1, [XU]>],
  93                                  [6, 8, 1, 1]>,
  94   InstrItinData<IIC_LdStLWARX,   [InstrStage<1, [XU]>],
  95                                  [82, 1, 1]>, // L2 latency
  96   InstrItinData<IIC_LdStSTD,     [InstrStage<1, [XU]>],
  97                                  [1, 1, 1]>,
  98   InstrItinData<IIC_LdStSTDU,    [InstrStage<1, [XU]>],
  99                                  [2, 1, 1, 1]>,
 100   InstrItinData<IIC_LdStSTDCX,   [InstrStage<1, [XU]>],
 101                                  [82, 1, 1]>, // L2 latency
 102   InstrItinData<IIC_LdStSTWCX,   [InstrStage<1, [XU]>],
 103                                  [82, 1, 1]>, // L2 latency
 104   InstrItinData<IIC_LdStSync,    [InstrStage<1, [XU]>],
 105                                  [6]>,
 106   InstrItinData<IIC_SprISYNC,    [InstrStage<1, [XU]>],
 107                                  [16]>,
 108   InstrItinData<IIC_SprMTMSR,    [InstrStage<1, [XU]>],
 109                                  [16, 1]>,
 110   InstrItinData<IIC_SprMFCR,     [InstrStage<1, [XU]>],
 111                                  [6, 1]>,
 112   InstrItinData<IIC_SprMFMSR,    [InstrStage<1, [XU]>],
 113                                  [4, 1]>,
 114   InstrItinData<IIC_SprMFSPR,    [InstrStage<1, [XU]>],
 115                                  [6, 1]>,
 116   InstrItinData<IIC_SprMFTB,     [InstrStage<1, [XU]>],
 117                                  [4, 1]>,
 118   InstrItinData<IIC_SprMTSPR,    [InstrStage<1, [XU]>],
 119                                  [6, 1]>,
 120   InstrItinData<IIC_SprRFI,      [InstrStage<1, [XU]>],
 121                                  [16]>,
 122   InstrItinData<IIC_SprSC,       [InstrStage<1, [XU]>],
 123                                  [16]>,
 124   InstrItinData<IIC_FPGeneral,   [InstrStage<1, [FU]>],
 125                                  [6, 1, 1]>,
 126   InstrItinData<IIC_FPAddSub,    [InstrStage<1, [FU]>],
 127                                  [6, 1, 1]>,
 128   InstrItinData<IIC_FPCompare,   [InstrStage<1, [FU]>],
 129                                  [5, 1, 1]>,
 130   InstrItinData<IIC_FPDivD,      [InstrStage<1, [FU]>],
 131                                  [72, 1, 1]>,
 132   InstrItinData<IIC_FPDivS,      [InstrStage<1, [FU]>],
 133                                  [59, 1, 1]>,
 134   InstrItinData<IIC_FPSqrt,      [InstrStage<1, [FU]>],
 135                                  [69, 1, 1]>,
 136   InstrItinData<IIC_FPFused,     [InstrStage<1, [FU]>],
 137                                  [6, 1, 1, 1]>,
 138   InstrItinData<IIC_FPRes,       [InstrStage<1, [FU]>],
 139                                  [6, 1]>
 140 ]>;
 141
 142 // ===---------------------------------------------------------------------===//
 143 // A2 machine model for scheduling and other instruction cost heuristics.
 144
 145 def PPCA2Model : SchedMachineModel {
 146   let IssueWidth = 1;  // 1 instruction is dispatched per cycle.
 147   let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
 148   let LoadLatency = 6; // Optimistic load latency assuming bypass.
 149                        // This is overriden by OperandCycles if the
 150                        // Itineraries are queried instead.
 151   let MispredictPenalty = 13;
 152
 153   let Itineraries = PPCA2Itineraries;
 154 }
 155