lib/Target/PowerPC/PPCScheduleE5500.td

   1 //===-- PPCScheduleE500mc.td - e5500 Scheduling Defs -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the Freescale e5500 64-bit
  11 // Power processor.
  12 //
  13 // All information is derived from the "e5500 Core Reference Manual",
  14 // Freescale Document Number e5500RM, Rev. 1, 03/2012.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 // Relevant functional units in the Freescale e5500 core
  18 // (These are the same as for the e500mc)
  19 //
  20 //  * Decode & Dispatch
  21 //    Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
  22 //    queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
  23 def E5500_DIS0 : FuncUnit;
  24 def E5500_DIS1 : FuncUnit;
  25
  26 //  * Execute
  27 //    6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
  28 //    The CFX has a bypass path, allowing non-divide instructions to execute
  29 //    while a divide instruction is being executed.
  30 def E5500_SFX0  : FuncUnit; // Simple unit 0
  31 def E5500_SFX1  : FuncUnit; // Simple unit 1
  32 def E5500_BU    : FuncUnit; // Branch unit
  33 def E5500_CFX_DivBypass
  34                 : FuncUnit; // CFX divide bypass path
  35 def E5500_CFX_0 : FuncUnit; // CFX pipeline stage 0
  36
  37 def E5500_CFX_1 : FuncUnit; // CFX pipeline stage 1
  38
  39 def E5500_LSU_0 : FuncUnit; // LSU pipeline
  40 def E5500_FPU_0 : FuncUnit; // FPU pipeline
  41
  42 def E5500_GPR_Bypass : Bypass;
  43 def E5500_FPR_Bypass : Bypass;
  44 def E5500_CR_Bypass  : Bypass;
  45
  46 def PPCE5500Itineraries : ProcessorItineraries<
  47   [E5500_DIS0, E5500_DIS1, E5500_SFX0, E5500_SFX1, E5500_BU,
  48    E5500_CFX_DivBypass, E5500_CFX_0, E5500_CFX_1,
  49    E5500_LSU_0, E5500_FPU_0],
  50   [E5500_CR_Bypass, E5500_GPR_Bypass, E5500_FPR_Bypass], [
  51   InstrItinData<IIC_IntSimple,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  52                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
  53                                  [5, 2, 2], // Latency = 1
  54                                  [E5500_GPR_Bypass,
  55                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  56   InstrItinData<IIC_IntGeneral,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  57                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
  58                                  [5, 2, 2], // Latency = 1
  59                                  [E5500_GPR_Bypass,
  60                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  61   InstrItinData<IIC_IntCompare,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  62                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
  63                                  [6, 2, 2], // Latency = 1 or 2
  64                                  [E5500_CR_Bypass,
  65                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  66   InstrItinData<IIC_IntDivD,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  67                                   InstrStage<1, [E5500_CFX_0], 0>,
  68                                   InstrStage<26, [E5500_CFX_DivBypass]>],
  69                                  [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
  70                                  [E5500_GPR_Bypass,
  71                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  72   InstrItinData<IIC_IntDivW,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  73                                   InstrStage<1, [E5500_CFX_0], 0>,
  74                                   InstrStage<16, [E5500_CFX_DivBypass]>],
  75                                  [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
  76                                  [E5500_GPR_Bypass,
  77                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  78   InstrItinData<IIC_IntMFFS,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  79                                   InstrStage<1, [E5500_FPU_0]>],
  80                                  [11], // Latency = 7, Repeat rate = 1
  81                                  [E5500_FPR_Bypass]>,
  82   InstrItinData<IIC_IntMTFSB0,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  83                                   InstrStage<7, [E5500_FPU_0]>],
  84                                  [11, 2, 2], // Latency = 7, Repeat rate = 7
  85                                  [NoBypass, NoBypass, NoBypass]>,
  86   InstrItinData<IIC_IntMulHD,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  87                                   InstrStage<1, [E5500_CFX_0], 0>,
  88                                   InstrStage<2, [E5500_CFX_1]>],
  89                                  [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
  90                                  [E5500_GPR_Bypass,
  91                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  92   InstrItinData<IIC_IntMulHW,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  93                                   InstrStage<1, [E5500_CFX_0], 0>,
  94                                   InstrStage<1, [E5500_CFX_1]>],
  95                                  [8, 2, 2], // Latency = 4, Repeat rate = 1
  96                                  [E5500_GPR_Bypass,
  97                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
  98   InstrItinData<IIC_IntMulHWU,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
  99                                   InstrStage<1, [E5500_CFX_0], 0>,
 100                                   InstrStage<1, [E5500_CFX_1]>],
 101                                  [8, 2, 2], // Latency = 4, Repeat rate = 1
 102                                  [E5500_GPR_Bypass,
 103                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 104   InstrItinData<IIC_IntMulLI,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 105                                   InstrStage<1, [E5500_CFX_0], 0>,
 106                                   InstrStage<2, [E5500_CFX_1]>],
 107                                  [8, 2, 2], // Latency = 4 or 5, Repeat = 2
 108                                  [E5500_GPR_Bypass,
 109                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 110   InstrItinData<IIC_IntRotate,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 111                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
 112                                  [5, 2, 2], // Latency = 1
 113                                  [E5500_GPR_Bypass,
 114                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 115   InstrItinData<IIC_IntRotateD,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 116                                   InstrStage<2, [E5500_SFX0, E5500_SFX1]>],
 117                                  [6, 2, 2], // Latency = 2, Repeat rate = 2
 118                                  [E5500_GPR_Bypass,
 119                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 120   InstrItinData<IIC_IntRotateDI, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 121                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
 122                                  [5, 2, 2], // Latency = 1, Repeat rate = 1
 123                                  [E5500_GPR_Bypass,
 124                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 125   InstrItinData<IIC_IntShift,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 126                                   InstrStage<2, [E5500_SFX0, E5500_SFX1]>],
 127                                  [6, 2, 2], // Latency = 2, Repeat rate = 2
 128                                  [E5500_GPR_Bypass,
 129                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 130   InstrItinData<IIC_IntTrapW,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 131                                   InstrStage<2, [E5500_SFX0]>],
 132                                  [6, 2], // Latency = 2, Repeat rate = 2
 133                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 134   InstrItinData<IIC_BrB,         [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 135                                   InstrStage<1, [E5500_BU]>],
 136                                  [5, 2], // Latency = 1
 137                                  [NoBypass, E5500_GPR_Bypass]>,
 138   InstrItinData<IIC_BrCR,        [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 139                                   InstrStage<1, [E5500_BU]>],
 140                                  [5, 2, 2], // Latency = 1
 141                                  [E5500_CR_Bypass,
 142                                   E5500_CR_Bypass, E5500_CR_Bypass]>,
 143   InstrItinData<IIC_BrMCR,       [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 144                                   InstrStage<1, [E5500_BU]>],
 145                                  [5, 2], // Latency = 1
 146                                  [E5500_CR_Bypass, E5500_CR_Bypass]>,
 147   InstrItinData<IIC_BrMCRX,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 148                                   InstrStage<1, [E5500_CFX_0]>],
 149                                  [5, 2, 2], // Latency = 1
 150                                  [E5500_CR_Bypass, E5500_GPR_Bypass]>,
 151   InstrItinData<IIC_LdStDCBA,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 152                                   InstrStage<1, [E5500_LSU_0]>],
 153                                  [7, 2], // Latency = 3, Repeat rate = 1
 154                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 155   InstrItinData<IIC_LdStDCBF,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 156                                   InstrStage<1, [E5500_LSU_0]>],
 157                                  [7, 2], // Latency = 3, Repeat rate = 1
 158                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 159   InstrItinData<IIC_LdStDCBI,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 160                                   InstrStage<1, [E5500_LSU_0]>],
 161                                  [7, 2], // Latency = 3, Repeat rate = 1
 162                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 163   InstrItinData<IIC_LdStLoad,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 164                                   InstrStage<1, [E5500_LSU_0]>],
 165                                  [7, 2], // Latency = 3
 166                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 167   InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 168                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 169                                   InstrStage<1, [E5500_LSU_0]>],
 170                                  [7, 2], // Latency = 3, Repeat rate = 1
 171                                  [E5500_GPR_Bypass, E5500_GPR_Bypass],
 172                                  2>, // 2 micro-ops
 173   InstrItinData<IIC_LdStLD,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 174                                   InstrStage<1, [E5500_LSU_0]>],
 175                                  [7, 2], // Latency = 3, Repeat rate = 1
 176                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 177   InstrItinData<IIC_LdStLDARX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 178                                   InstrStage<3, [E5500_LSU_0]>],
 179                                  [7, 2], // Latency = 3, Repeat rate = 3
 180                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 181   InstrItinData<IIC_LdStLDU,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 182                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 183                                   InstrStage<1, [E5500_LSU_0]>],
 184                                  [7, 2], // Latency = 3, Repeat rate = 1
 185                                  [E5500_GPR_Bypass, E5500_GPR_Bypass],
 186                                  2>, // 2 micro-ops
 187   InstrItinData<IIC_LdStStore,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 188                                   InstrStage<1, [E5500_LSU_0]>],
 189                                  [7, 2], // Latency = 3, Repeat rate = 1
 190                                  [NoBypass, E5500_GPR_Bypass]>,
 191   InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 192                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 193                                   InstrStage<1, [E5500_LSU_0]>],
 194                                  [7, 2], // Latency = 3, Repeat rate = 1
 195                                  [NoBypass, E5500_GPR_Bypass],
 196                                  2>, // 2 micro-ops
 197   InstrItinData<IIC_LdStICBI,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 198                                   InstrStage<1, [E5500_LSU_0]>],
 199                                  [7, 2], // Latency = 3, Repeat rate = 1
 200                                  [NoBypass, E5500_GPR_Bypass]>,
 201   InstrItinData<IIC_LdStSTFD,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 202                                   InstrStage<1, [E5500_LSU_0]>],
 203                                  [7, 2, 2], // Latency = 3, Repeat rate = 1
 204                                  [E5500_GPR_Bypass,
 205                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 206   InstrItinData<IIC_LdStSTFDU,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 207                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 208                                   InstrStage<1, [E5500_LSU_0]>],
 209                                  [7, 2, 2], // Latency = 3, Repeat rate = 1
 210                                  [E5500_GPR_Bypass,
 211                                   E5500_GPR_Bypass, E5500_GPR_Bypass],
 212                                  2>, // 2 micro-ops
 213   InstrItinData<IIC_LdStLFD,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 214                                   InstrStage<1, [E5500_LSU_0]>],
 215                                  [8, 2, 2], // Latency = 4, Repeat rate = 1
 216                                  [E5500_FPR_Bypass,
 217                                   E5500_GPR_Bypass, E5500_GPR_Bypass],
 218                                  2>, // 2 micro-ops
 219   InstrItinData<IIC_LdStLFDU,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 220                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 221                                   InstrStage<1, [E5500_LSU_0]>],
 222                                  [8, 2, 2], // Latency = 4, Repeat rate = 1
 223                                  [E5500_FPR_Bypass,
 224                                   E5500_GPR_Bypass, E5500_GPR_Bypass],
 225                                  2>, // 2 micro-ops
 226   InstrItinData<IIC_LdStLHA,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 227                                   InstrStage<1, [E5500_LSU_0]>],
 228                                  [7, 2], // Latency = 3
 229                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 230   InstrItinData<IIC_LdStLHAU,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 231                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 232                                   InstrStage<1, [E5500_LSU_0]>],
 233                                  [7, 2], // Latency = 3, Repeat rate = 1
 234                                  [E5500_GPR_Bypass, E5500_GPR_Bypass],
 235                                  2>, // 2 micro-ops
 236   InstrItinData<IIC_LdStLMW,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 237                                   InstrStage<4, [E5500_LSU_0]>],
 238                                  [8, 2], // Latency = r+3, Repeat rate = r+3
 239                                  [NoBypass, E5500_GPR_Bypass]>,
 240   InstrItinData<IIC_LdStLWARX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 241                                   InstrStage<3, [E5500_LSU_0]>],
 242                                  [7, 2, 2], // Latency = 3, Repeat rate = 3
 243                                  [E5500_GPR_Bypass,
 244                                   E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 245   InstrItinData<IIC_LdStSTD,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 246                                   InstrStage<1, [E5500_LSU_0]>],
 247                                  [7, 2], // Latency = 3, Repeat rate = 1
 248                                  [NoBypass, E5500_GPR_Bypass]>,
 249   InstrItinData<IIC_LdStSTDCX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 250                                   InstrStage<1, [E5500_LSU_0]>],
 251                                  [7, 2], // Latency = 3, Repeat rate = 1
 252                                  [NoBypass, E5500_GPR_Bypass]>,
 253   InstrItinData<IIC_LdStSTDU,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 254                                   InstrStage<1, [E5500_SFX0, E5500_SFX1], 0>,
 255                                   InstrStage<1, [E5500_LSU_0]>],
 256                                  [7, 2], // Latency = 3, Repeat rate = 1
 257                                  [NoBypass, E5500_GPR_Bypass],
 258                                  2>, // 2 micro-ops
 259   InstrItinData<IIC_LdStSTWCX,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 260                                   InstrStage<1, [E5500_LSU_0]>],
 261                                  [7, 2], // Latency = 3, Repeat rate = 1
 262                                  [NoBypass, E5500_GPR_Bypass]>,
 263   InstrItinData<IIC_LdStSync,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 264                                   InstrStage<1, [E5500_LSU_0]>]>,
 265   InstrItinData<IIC_SprMTMSR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 266                                   InstrStage<2, [E5500_CFX_0]>],
 267                                  [6, 2], // Latency = 2, Repeat rate = 4
 268                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 269   InstrItinData<IIC_SprTLBSYNC,  [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 270                                   InstrStage<1, [E5500_LSU_0], 0>]>,
 271   InstrItinData<IIC_SprMFCR,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 272                                   InstrStage<5, [E5500_CFX_0]>],
 273                                  [9, 2], // Latency = 5, Repeat rate = 5
 274                                  [E5500_GPR_Bypass, E5500_CR_Bypass]>,
 275   InstrItinData<IIC_SprMFMSR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 276                                   InstrStage<4, [E5500_SFX0]>],
 277                                  [8, 2], // Latency = 4, Repeat rate = 4
 278                                  [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
 279   InstrItinData<IIC_SprMFSPR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 280                                   InstrStage<1, [E5500_CFX_0]>],
 281                                  [5], // Latency = 1, Repeat rate = 1
 282                                  [E5500_GPR_Bypass]>,
 283   InstrItinData<IIC_SprMFTB,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 284                                   InstrStage<4, [E5500_CFX_0]>],
 285                                  [8, 2], // Latency = 4, Repeat rate = 4
 286                                  [NoBypass, E5500_GPR_Bypass]>,
 287   InstrItinData<IIC_SprMTSPR,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 288                                   InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
 289                                  [5], // Latency = 1, Repeat rate = 1
 290                                  [E5500_GPR_Bypass]>,
 291   InstrItinData<IIC_FPGeneral,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 292                                   InstrStage<1, [E5500_FPU_0]>],
 293                                  [11, 2, 2], // Latency = 7, Repeat rate = 1
 294                                  [E5500_FPR_Bypass,
 295                                   E5500_FPR_Bypass, E5500_FPR_Bypass]>,
 296   InstrItinData<IIC_FPAddSub,    [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 297                                   InstrStage<1, [E5500_FPU_0]>],
 298                                  [11, 2, 2], // Latency = 7, Repeat rate = 1
 299                                  [E5500_FPR_Bypass,
 300                                   E5500_FPR_Bypass, E5500_FPR_Bypass]>,
 301   InstrItinData<IIC_FPCompare,   [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 302                                   InstrStage<1, [E5500_FPU_0]>],
 303                                  [11, 2, 2], // Latency = 7, Repeat rate = 1
 304                                  [E5500_CR_Bypass,
 305                                   E5500_FPR_Bypass, E5500_FPR_Bypass]>,
 306   InstrItinData<IIC_FPDivD,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 307                                   InstrStage<31, [E5500_FPU_0]>],
 308                                  [39, 2, 2], // Latency = 35, Repeat rate = 31
 309                                  [E5500_FPR_Bypass,
 310                                   E5500_FPR_Bypass, E5500_FPR_Bypass]>,
 311   InstrItinData<IIC_FPDivS,      [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 312                                   InstrStage<16, [E5500_FPU_0]>],
 313                                  [24, 2, 2], // Latency = 20, Repeat rate = 16
 314                                  [E5500_FPR_Bypass,
 315                                   E5500_FPR_Bypass, E5500_FPR_Bypass]>,
 316   InstrItinData<IIC_FPFused,     [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 317                                   InstrStage<1, [E5500_FPU_0]>],
 318                                  [11, 2, 2, 2], // Latency = 7, Repeat rate = 1
 319                                  [E5500_FPR_Bypass,
 320                                   E5500_FPR_Bypass, E5500_FPR_Bypass,
 321                                   E5500_FPR_Bypass]>,
 322   InstrItinData<IIC_FPRes,       [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
 323                                   InstrStage<2, [E5500_FPU_0]>],
 324                                  [12, 2], // Latency = 8, Repeat rate = 2
 325                                  [E5500_FPR_Bypass, E5500_FPR_Bypass]>
 326 ]>;
 327
 328 // ===---------------------------------------------------------------------===//
 329 // e5500 machine model for scheduling and other instruction cost heuristics.
 330
 331 def PPCE5500Model : SchedMachineModel {
 332   let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
 333   let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
 334   let LoadLatency = 6; // Optimistic load latency assuming bypass.
 335                        // This is overriden by OperandCycles if the
 336                        // Itineraries are queried instead.
 337
 338   let Itineraries = PPCE5500Itineraries;
 339 }