1 //===-- PPCScheduleG4.td - PPC G4 Scheduling Definitions ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the G4 (7400) processor.
12 //===----------------------------------------------------------------------===//
14 def G4Itineraries : ProcessorItineraries<
15 [IU1, IU2, SLU, SRU, BPU, FPU1, VIU1, VIU2, VPU, VFPU], [], [
16 InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>,
17 InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
18 InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
19 InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
20 InstrItinData<IntMFFS , [InstrStage<3, [FPU1]>]>,
21 InstrItinData<IntMFVSCR , [InstrStage<1, [VIU1]>]>,
22 InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
23 InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
24 InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
25 InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
26 InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>,
27 InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>,
28 InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
29 InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
30 InstrItinData<BrCR , [InstrStage<1, [SRU]>]>,
31 InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>,
32 InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>,
33 InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>,
34 InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>,
35 InstrItinData<LdStLoad , [InstrStage<2, [SLU]>]>,
36 InstrItinData<LdStLoadUpd , [InstrStage<2, [SLU]>]>,
37 InstrItinData<LdStStore , [InstrStage<2, [SLU]>]>,
38 InstrItinData<LdStStoreUpd, [InstrStage<2, [SLU]>]>,
39 InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>,
40 InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>,
41 InstrItinData<LdStSTFD , [InstrStage<2, [SLU]>]>,
42 InstrItinData<LdStSTFDU , [InstrStage<2, [SLU]>]>,
43 InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
44 InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
45 InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
46 InstrItinData<LdStLHAU , [InstrStage<2, [SLU]>]>,
47 InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
48 InstrItinData<LdStLVecX , [InstrStage<2, [SLU]>]>,
49 InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
50 InstrItinData<LdStSTVEBX , [InstrStage<2, [SLU]>]>,
51 InstrItinData<LdStSTWCX , [InstrStage<5, [SLU]>]>,
52 InstrItinData<LdStSync , [InstrStage<8, [SLU]>]>,
53 InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>,
54 InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>,
55 InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>,
56 InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>,
57 InstrItinData<SprTLBSYNC , [InstrStage<8, [SRU]>]>,
58 InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>,
59 InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>,
60 InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>,
61 InstrItinData<SprMFTB , [InstrStage<1, [SRU]>]>,
62 InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>,
63 InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>,
64 InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>,
65 InstrItinData<SprSC , [InstrStage<2, [SRU]>]>,
66 InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>,
67 InstrItinData<FPAddSub , [InstrStage<1, [FPU1]>]>,
68 InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>,
69 InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>,
70 InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
71 InstrItinData<FPFused , [InstrStage<1, [FPU1]>]>,
72 InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>,
73 InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
74 InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
75 InstrItinData<VecFPCompare, [InstrStage<1, [VIU1]>]>,
76 InstrItinData<VecComplex , [InstrStage<3, [VIU2]>]>,
77 InstrItinData<VecPerm , [InstrStage<1, [VPU]>]>,
78 InstrItinData<VecFPRound , [InstrStage<4, [VFPU]>]>,
79 InstrItinData<VecVSL , [InstrStage<1, [VIU1]>]>,
80 InstrItinData<VecVSR , [InstrStage<1, [VIU1]>]>