1 //===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the G4+ (7450) processor.
12 //===----------------------------------------------------------------------===//
14 def IU3 : FuncUnit; // integer unit 3 (7450 simple)
15 def IU4 : FuncUnit; // integer unit 4 (7450 simple)
17 def G4PlusItineraries : ProcessorItineraries<
18 [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [
19 InstrItinData<IIC_IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
20 InstrItinData<IIC_IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
21 InstrItinData<IIC_IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
22 InstrItinData<IIC_IntDivW , [InstrStage<23, [IU2]>]>,
23 InstrItinData<IIC_IntMFFS , [InstrStage<5, [FPU1]>]>,
24 InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [VFPU]>]>,
25 InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
26 InstrItinData<IIC_IntMulHW , [InstrStage<4, [IU2]>]>,
27 InstrItinData<IIC_IntMulHWU , [InstrStage<4, [IU2]>]>,
28 InstrItinData<IIC_IntMulLI , [InstrStage<3, [IU2]>]>,
29 InstrItinData<IIC_IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
30 InstrItinData<IIC_IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
31 InstrItinData<IIC_IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
32 InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>,
33 InstrItinData<IIC_BrCR , [InstrStage<2, [IU2]>]>,
34 InstrItinData<IIC_BrMCR , [InstrStage<2, [IU2]>]>,
35 InstrItinData<IIC_BrMCRX , [InstrStage<2, [IU2]>]>,
36 InstrItinData<IIC_LdStDCBF , [InstrStage<3, [SLU]>]>,
37 InstrItinData<IIC_LdStDCBI , [InstrStage<3, [SLU]>]>,
38 InstrItinData<IIC_LdStLoad , [InstrStage<3, [SLU]>]>,
39 InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [SLU]>]>,
40 InstrItinData<IIC_LdStStore , [InstrStage<3, [SLU]>]>,
41 InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [SLU]>]>,
42 InstrItinData<IIC_LdStDSS , [InstrStage<3, [SLU]>]>,
43 InstrItinData<IIC_LdStICBI , [InstrStage<3, [IU2]>]>,
44 InstrItinData<IIC_LdStSTFD , [InstrStage<3, [SLU]>]>,
45 InstrItinData<IIC_LdStSTFDU , [InstrStage<3, [SLU]>]>,
46 InstrItinData<IIC_LdStLFD , [InstrStage<4, [SLU]>]>,
47 InstrItinData<IIC_LdStLFDU , [InstrStage<4, [SLU]>]>,
48 InstrItinData<IIC_LdStLHA , [InstrStage<3, [SLU]>]>,
49 InstrItinData<IIC_LdStLHAU , [InstrStage<3, [SLU]>]>,
50 InstrItinData<IIC_LdStLMW , [InstrStage<37, [SLU]>]>,
51 InstrItinData<IIC_LdStLVecX , [InstrStage<3, [SLU]>]>,
52 InstrItinData<IIC_LdStLWA , [InstrStage<3, [SLU]>]>,
53 InstrItinData<IIC_LdStLWARX , [InstrStage<3, [SLU]>]>,
54 InstrItinData<IIC_LdStSTD , [InstrStage<3, [SLU]>]>,
55 InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [SLU]>]>,
56 InstrItinData<IIC_LdStSTDU , [InstrStage<3, [SLU]>]>,
57 InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [SLU]>]>,
58 InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [SLU]>]>,
59 InstrItinData<IIC_LdStSync , [InstrStage<35, [SLU]>]>,
60 InstrItinData<IIC_SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
61 InstrItinData<IIC_SprMFSR , [InstrStage<4, [IU2]>]>,
62 InstrItinData<IIC_SprMTMSR , [InstrStage<2, [IU2]>]>,
63 InstrItinData<IIC_SprMTSR , [InstrStage<2, [IU2]>]>,
64 InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [SLU]>]>,
65 InstrItinData<IIC_SprMFCR , [InstrStage<2, [IU2]>]>,
66 InstrItinData<IIC_SprMFMSR , [InstrStage<3, [IU2]>]>,
67 InstrItinData<IIC_SprMFSPR , [InstrStage<4, [IU2]>]>,
68 InstrItinData<IIC_SprMFTB , [InstrStage<5, [IU2]>]>,
69 InstrItinData<IIC_SprMTSPR , [InstrStage<2, [IU2]>]>,
70 InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [IU2]>]>,
71 InstrItinData<IIC_SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
72 InstrItinData<IIC_SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
73 InstrItinData<IIC_FPGeneral , [InstrStage<5, [FPU1]>]>,
74 InstrItinData<IIC_FPAddSub , [InstrStage<5, [FPU1]>]>,
75 InstrItinData<IIC_FPCompare , [InstrStage<5, [FPU1]>]>,
76 InstrItinData<IIC_FPDivD , [InstrStage<35, [FPU1]>]>,
77 InstrItinData<IIC_FPDivS , [InstrStage<21, [FPU1]>]>,
78 InstrItinData<IIC_FPFused , [InstrStage<5, [FPU1]>]>,
79 InstrItinData<IIC_FPRes , [InstrStage<14, [FPU1]>]>,
80 InstrItinData<IIC_VecGeneral , [InstrStage<1, [VIU1]>]>,
81 InstrItinData<IIC_VecFP , [InstrStage<4, [VFPU]>]>,
82 InstrItinData<IIC_VecFPCompare, [InstrStage<2, [VFPU]>]>,
83 InstrItinData<IIC_VecComplex , [InstrStage<4, [VIU2]>]>,
84 InstrItinData<IIC_VecPerm , [InstrStage<2, [VPU]>]>,
85 InstrItinData<IIC_VecFPRound , [InstrStage<4, [VIU1]>]>,
86 InstrItinData<IIC_VecVSL , [InstrStage<2, [VPU]>]>,
87 InstrItinData<IIC_VecVSR , [InstrStage<2, [VPU]>]>