1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/IR/Attributes.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/Host.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Target/TargetMachine.h"
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #define GET_SUBTARGETINFO_CTOR
28 #include "PPCGenSubtargetInfo.inc"
32 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
33 const std::string &FS, bool is64Bit)
34 : PPCGenSubtargetInfo(TT, CPU, FS)
37 initializeEnvironment();
38 resetSubtargetFeatures(CPU, FS);
41 /// SetJITMode - This is called to inform the subtarget info that we are
42 /// producing code for the JIT.
43 void PPCSubtarget::SetJITMode() {
44 // JIT mode doesn't want lazy resolver stubs, it knows exactly where
45 // everything is. This matters for PPC64, which codegens in PIC mode without
47 HasLazyResolverStubs = false;
49 // Calls to external functions need to use indirect calls
50 IsJITCodeModel = true;
53 void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
54 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
55 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
57 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
60 !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
62 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
64 initializeEnvironment();
65 resetSubtargetFeatures(CPU, FS);
69 void PPCSubtarget::initializeEnvironment() {
71 DarwinDirective = PPC::DIR_NONE;
73 Has64BitSupport = false;
91 HasLazyResolverStubs = false;
92 IsJITCodeModel = false;
95 void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
96 // Determine default and user specified characteristics
97 std::string CPUName = CPU;
100 #if (defined(__APPLE__) || defined(__linux__)) && \
101 (defined(__ppc__) || defined(__powerpc__))
102 if (CPUName == "generic")
103 CPUName = sys::getHostCPUName();
106 // Initialize scheduling itinerary for the specified CPU.
107 InstrItins = getInstrItineraryForCPU(CPUName);
109 // Make sure 64-bit features are available when CPUname is generic
110 std::string FullFS = FS;
112 // If we are generating code for ppc64, verify that options make sense.
114 Has64BitSupport = true;
115 // Silently force 64-bit register use on ppc64.
118 FullFS = "+64bit," + FullFS;
123 // Parse features string.
124 ParseSubtargetFeatures(CPUName, FullFS);
126 // If the user requested use of 64-bit regs, but the cpu selected doesn't
127 // support it, ignore.
128 if (use64BitRegs() && !has64BitSupport())
129 Use64BitRegs = false;
131 // Set up darwin-specific properties.
133 HasLazyResolverStubs = true;
135 // QPX requires a 32-byte aligned stack. Note that we need to do this if
136 // we're compiling for a BG/Q system regardless of whether or not QPX
137 // is enabled because external functions will assume this alignment.
138 if (hasQPX() || isBGQ())
141 // Determine endianness.
142 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
145 /// hasLazyResolverStub - Return true if accesses to the specified global have
146 /// to go through a dyld lazy resolution stub. This means that an extra load
147 /// is required to get the address of the global.
148 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
149 const TargetMachine &TM) const {
150 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
151 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
153 // If symbol visibility is hidden, the extra load is not needed if
154 // the symbol is definitely defined in the current translation unit.
155 bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
156 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
158 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
159 GV->hasCommonLinkage() || isDecl;
162 bool PPCSubtarget::enablePostRAScheduler(
163 CodeGenOpt::Level OptLevel,
164 TargetSubtargetInfo::AntiDepBreakMode& Mode,
165 RegClassVector& CriticalPathRCs) const {
166 // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here,
167 // but we can't because we can't reassign the cr registers. There is a
168 // dependence between the cr register and the RLWINM instruction used
169 // to extract its value which the anti-dependency breaker can't currently
170 // see. Maybe we should make a late-expanded pseudo to encode this dependency.
171 // (the relevant code is in PPCDAGToDAGISel::SelectSETCC)
173 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
175 CriticalPathRCs.clear();
178 CriticalPathRCs.push_back(&PPC::G8RCRegClass);
180 CriticalPathRCs.push_back(&PPC::GPRCRegClass);
182 CriticalPathRCs.push_back(&PPC::F8RCRegClass);
183 CriticalPathRCs.push_back(&PPC::VRRCRegClass);
185 return OptLevel >= CodeGenOpt::Default;