1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetMachine.h"
29 #define DEBUG_TYPE "ppc-subtarget"
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "PPCGenSubtargetInfo.inc"
35 /// Return the datalayout string of a subtarget.
36 static std::string getDataLayoutString(const Triple &T) {
37 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
40 // Most PPC* platforms are big endian, PPC64LE is little endian.
41 if (T.getArch() == Triple::ppc64le)
46 Ret += DataLayout::getManglingComponent(T);
48 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
50 if (!is64Bit || T.getOS() == Triple::Lv2)
53 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
54 // documentation are wrong; these are correct (i.e. "what gcc does").
55 if (is64Bit || !T.isOSDarwin())
60 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
69 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
71 initializeEnvironment();
72 initSubtargetFeatures(CPU, FS);
76 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
77 const std::string &FS, const PPCTargetMachine &TM)
78 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
79 DL(getDataLayoutString(TargetTriple)),
80 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
81 TargetTriple.getArch() == Triple::ppc64le),
82 TargetABI(PPC_ABI_UNKNOWN),
83 FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this),
84 TLInfo(TM), TSInfo(&DL) {}
86 void PPCSubtarget::initializeEnvironment() {
88 DarwinDirective = PPC::DIR_NONE;
90 Has64BitSupport = false;
104 HasRecipPrec = false;
113 HasOnlyMSYNC = false;
117 DeprecatedMFTB = false;
118 DeprecatedDST = false;
119 HasLazyResolverStubs = false;
122 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
123 // Determine default and user specified characteristics
124 std::string CPUName = CPU;
127 #if (defined(__APPLE__) || defined(__linux__)) && \
128 (defined(__ppc__) || defined(__powerpc__))
129 if (CPUName == "generic")
130 CPUName = sys::getHostCPUName();
133 // Initialize scheduling itinerary for the specified CPU.
134 InstrItins = getInstrItineraryForCPU(CPUName);
136 // Parse features string.
137 ParseSubtargetFeatures(CPUName, FS);
139 // If the user requested use of 64-bit regs, but the cpu selected doesn't
140 // support it, ignore.
141 if (IsPPC64 && has64BitSupport())
144 // Set up darwin-specific properties.
146 HasLazyResolverStubs = true;
148 // QPX requires a 32-byte aligned stack. Note that we need to do this if
149 // we're compiling for a BG/Q system regardless of whether or not QPX
150 // is enabled because external functions will assume this alignment.
151 if (hasQPX() || isBGQ())
154 // Determine endianness.
155 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
157 // Determine default ABI.
158 if (TargetABI == PPC_ABI_UNKNOWN) {
159 if (!isDarwin() && IsPPC64) {
161 TargetABI = PPC_ABI_ELFv2;
163 TargetABI = PPC_ABI_ELFv1;
168 /// hasLazyResolverStub - Return true if accesses to the specified global have
169 /// to go through a dyld lazy resolution stub. This means that an extra load
170 /// is required to get the address of the global.
171 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
172 const TargetMachine &TM) const {
173 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
174 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
176 bool isDecl = GV->isDeclaration();
177 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
179 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
180 GV->hasCommonLinkage() || isDecl;
183 // Embedded cores need aggressive scheduling (and some others also benefit).
184 static bool needsAggressiveScheduling(unsigned Directive) {
186 default: return false;
189 case PPC::DIR_E500mc:
197 bool PPCSubtarget::enableMachineScheduler() const {
198 // Enable MI scheduling for the embedded cores.
199 // FIXME: Enable this for all cores (some additional modeling
200 // may be necessary).
201 return needsAggressiveScheduling(DarwinDirective);
204 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
205 bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
207 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
208 return TargetSubtargetInfo::ANTIDEP_ALL;
211 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
212 CriticalPathRCs.clear();
213 CriticalPathRCs.push_back(isPPC64() ?
214 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
217 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
220 unsigned NumRegionInstrs) const {
221 if (needsAggressiveScheduling(DarwinDirective)) {
222 Policy.OnlyTopDown = false;
223 Policy.OnlyBottomUp = false;
226 // Spilling is generally expensive on all PPC cores, so always enable
227 // register-pressure tracking.
228 Policy.ShouldTrackPressure = true;
231 bool PPCSubtarget::useAA() const {
232 // Use AA during code generation for the embedded cores.
233 return needsAggressiveScheduling(DarwinDirective);