1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetMachine.h"
29 #define DEBUG_TYPE "ppc-subtarget"
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "PPCGenSubtargetInfo.inc"
35 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
37 initializeEnvironment();
38 resetSubtargetFeatures(CPU, FS);
42 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
43 const std::string &FS, bool is64Bit,
44 CodeGenOpt::Level OptLevel)
45 : PPCGenSubtargetInfo(TT, CPU, FS), IsPPC64(is64Bit), TargetTriple(TT),
47 FrameLowering(initializeSubtargetDependencies(CPU, FS)) {}
49 /// SetJITMode - This is called to inform the subtarget info that we are
50 /// producing code for the JIT.
51 void PPCSubtarget::SetJITMode() {
52 // JIT mode doesn't want lazy resolver stubs, it knows exactly where
53 // everything is. This matters for PPC64, which codegens in PIC mode without
55 HasLazyResolverStubs = false;
57 // Calls to external functions need to use indirect calls
58 IsJITCodeModel = true;
61 void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
62 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
63 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
65 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
68 !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
70 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
72 initializeEnvironment();
73 resetSubtargetFeatures(CPU, FS);
77 void PPCSubtarget::initializeEnvironment() {
79 DarwinDirective = PPC::DIR_NONE;
81 Has64BitSupport = false;
102 DeprecatedMFTB = false;
103 DeprecatedDST = false;
104 HasLazyResolverStubs = false;
105 IsJITCodeModel = false;
108 void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
109 // Determine default and user specified characteristics
110 std::string CPUName = CPU;
113 #if (defined(__APPLE__) || defined(__linux__)) && \
114 (defined(__ppc__) || defined(__powerpc__))
115 if (CPUName == "generic")
116 CPUName = sys::getHostCPUName();
119 // Initialize scheduling itinerary for the specified CPU.
120 InstrItins = getInstrItineraryForCPU(CPUName);
122 // Make sure 64-bit features are available when CPUname is generic
123 std::string FullFS = FS;
125 // If we are generating code for ppc64, verify that options make sense.
127 Has64BitSupport = true;
128 // Silently force 64-bit register use on ppc64.
131 FullFS = "+64bit," + FullFS;
136 // At -O2 and above, track CR bits as individual registers.
137 if (OptLevel >= CodeGenOpt::Default) {
139 FullFS = "+crbits," + FullFS;
144 // Parse features string.
145 ParseSubtargetFeatures(CPUName, FullFS);
147 // If the user requested use of 64-bit regs, but the cpu selected doesn't
148 // support it, ignore.
149 if (use64BitRegs() && !has64BitSupport())
150 Use64BitRegs = false;
152 // Set up darwin-specific properties.
154 HasLazyResolverStubs = true;
156 // QPX requires a 32-byte aligned stack. Note that we need to do this if
157 // we're compiling for a BG/Q system regardless of whether or not QPX
158 // is enabled because external functions will assume this alignment.
159 if (hasQPX() || isBGQ())
162 // Determine endianness.
163 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
165 // FIXME: For now, we disable VSX in little-endian mode until endian
166 // issues in those instructions can be addressed.
171 /// hasLazyResolverStub - Return true if accesses to the specified global have
172 /// to go through a dyld lazy resolution stub. This means that an extra load
173 /// is required to get the address of the global.
174 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
175 const TargetMachine &TM) const {
176 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
177 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
179 // If symbol visibility is hidden, the extra load is not needed if
180 // the symbol is definitely defined in the current translation unit.
181 bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
182 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
184 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
185 GV->hasCommonLinkage() || isDecl;
188 bool PPCSubtarget::enablePostRAScheduler(
189 CodeGenOpt::Level OptLevel,
190 TargetSubtargetInfo::AntiDepBreakMode& Mode,
191 RegClassVector& CriticalPathRCs) const {
192 Mode = TargetSubtargetInfo::ANTIDEP_ALL;
194 CriticalPathRCs.clear();
197 CriticalPathRCs.push_back(&PPC::G8RCRegClass);
199 CriticalPathRCs.push_back(&PPC::GPRCRegClass);
201 return OptLevel >= CodeGenOpt::Default;
204 // Embedded cores need aggressive scheduling (and some others also benefit).
205 static bool needsAggressiveScheduling(unsigned Directive) {
207 default: return false;
210 case PPC::DIR_E500mc:
217 bool PPCSubtarget::enableMachineScheduler() const {
218 // Enable MI scheduling for the embedded cores.
219 // FIXME: Enable this for all cores (some additional modeling
220 // may be necessary).
221 return needsAggressiveScheduling(DarwinDirective);
224 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
227 unsigned NumRegionInstrs) const {
228 if (needsAggressiveScheduling(DarwinDirective)) {
229 Policy.OnlyTopDown = false;
230 Policy.OnlyBottomUp = false;
233 // Spilling is generally expensive on all PPC cores, so always enable
234 // register-pressure tracking.
235 Policy.ShouldTrackPressure = true;
238 bool PPCSubtarget::useAA() const {
239 // Use AA during code generation for the embedded cores.
240 return needsAggressiveScheduling(DarwinDirective);