1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetMachine.h"
29 #define DEBUG_TYPE "ppc-subtarget"
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "PPCGenSubtargetInfo.inc"
35 /// Return the datalayout string of a subtarget.
36 static std::string getDataLayoutString(const Triple &T) {
37 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
40 // Most PPC* platforms are big endian, PPC64LE is little endian.
41 if (T.getArch() == Triple::ppc64le)
46 Ret += DataLayout::getManglingComponent(T);
48 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
50 if (!is64Bit || T.getOS() == Triple::Lv2)
53 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
54 // documentation are wrong; these are correct (i.e. "what gcc does").
55 if (is64Bit || !T.isOSDarwin())
60 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
69 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
71 initializeEnvironment();
72 resetSubtargetFeatures(CPU, FS);
76 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
77 const std::string &FS, PPCTargetMachine &TM,
78 CodeGenOpt::Level OptLevel)
79 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
80 DL(getDataLayoutString(TargetTriple)),
81 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
82 TargetTriple.getArch() == Triple::ppc64le),
83 OptLevel(OptLevel), TargetABI(PPC_ABI_UNKNOWN),
84 FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this),
85 TLInfo(TM), TSInfo(&DL) {}
87 void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
88 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
89 Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
91 Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
94 !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
96 !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
98 initializeEnvironment();
99 resetSubtargetFeatures(CPU, FS);
103 void PPCSubtarget::initializeEnvironment() {
105 DarwinDirective = PPC::DIR_NONE;
107 Has64BitSupport = false;
108 Use64BitRegs = false;
120 HasRecipPrec = false;
132 DeprecatedMFTB = false;
133 DeprecatedDST = false;
134 HasLazyResolverStubs = false;
137 void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
138 // Determine default and user specified characteristics
139 std::string CPUName = CPU;
142 #if (defined(__APPLE__) || defined(__linux__)) && \
143 (defined(__ppc__) || defined(__powerpc__))
144 if (CPUName == "generic")
145 CPUName = sys::getHostCPUName();
148 // Initialize scheduling itinerary for the specified CPU.
149 InstrItins = getInstrItineraryForCPU(CPUName);
151 // Make sure 64-bit features are available when CPUname is generic
152 std::string FullFS = FS;
154 // If we are generating code for ppc64, verify that options make sense.
156 Has64BitSupport = true;
157 // Silently force 64-bit register use on ppc64.
160 FullFS = "+64bit," + FullFS;
165 // At -O2 and above, track CR bits as individual registers.
166 if (OptLevel >= CodeGenOpt::Default) {
168 FullFS = "+crbits," + FullFS;
173 // Parse features string.
174 ParseSubtargetFeatures(CPUName, FullFS);
176 // If the user requested use of 64-bit regs, but the cpu selected doesn't
177 // support it, ignore.
178 if (use64BitRegs() && !has64BitSupport())
179 Use64BitRegs = false;
181 // Set up darwin-specific properties.
183 HasLazyResolverStubs = true;
185 // QPX requires a 32-byte aligned stack. Note that we need to do this if
186 // we're compiling for a BG/Q system regardless of whether or not QPX
187 // is enabled because external functions will assume this alignment.
188 if (hasQPX() || isBGQ())
191 // Determine endianness.
192 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
194 // FIXME: For now, we disable VSX in little-endian mode until endian
195 // issues in those instructions can be addressed.
199 // Determine default ABI.
200 if (TargetABI == PPC_ABI_UNKNOWN) {
201 if (!isDarwin() && IsPPC64) {
203 TargetABI = PPC_ABI_ELFv2;
205 TargetABI = PPC_ABI_ELFv1;
210 /// hasLazyResolverStub - Return true if accesses to the specified global have
211 /// to go through a dyld lazy resolution stub. This means that an extra load
212 /// is required to get the address of the global.
213 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
214 const TargetMachine &TM) const {
215 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
216 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
218 // If symbol visibility is hidden, the extra load is not needed if
219 // the symbol is definitely defined in the current translation unit.
220 bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
221 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
223 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
224 GV->hasCommonLinkage() || isDecl;
227 // Embedded cores need aggressive scheduling (and some others also benefit).
228 static bool needsAggressiveScheduling(unsigned Directive) {
230 default: return false;
233 case PPC::DIR_E500mc:
241 bool PPCSubtarget::enableMachineScheduler() const {
242 // Enable MI scheduling for the embedded cores.
243 // FIXME: Enable this for all cores (some additional modeling
244 // may be necessary).
245 return needsAggressiveScheduling(DarwinDirective);
248 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
249 bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
251 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
252 return TargetSubtargetInfo::ANTIDEP_ALL;
255 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
256 CriticalPathRCs.clear();
257 CriticalPathRCs.push_back(isPPC64() ?
258 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
261 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
264 unsigned NumRegionInstrs) const {
265 if (needsAggressiveScheduling(DarwinDirective)) {
266 Policy.OnlyTopDown = false;
267 Policy.OnlyBottomUp = false;
270 // Spilling is generally expensive on all PPC cores, so always enable
271 // register-pressure tracking.
272 Policy.ShouldTrackPressure = true;
275 bool PPCSubtarget::useAA() const {
276 // Use AA during code generation for the embedded cores.
277 return needsAggressiveScheduling(DarwinDirective);