1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Host.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetMachine.h"
31 #define DEBUG_TYPE "ppc-subtarget"
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #define GET_SUBTARGETINFO_CTOR
35 #include "PPCGenSubtargetInfo.inc"
37 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
38 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
40 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
41 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
44 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
46 initializeEnvironment();
47 initSubtargetFeatures(CPU, FS);
51 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
52 const std::string &FS, const PPCTargetMachine &TM)
53 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
54 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
55 TargetTriple.getArch() == Triple::ppc64le),
56 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
57 InstrInfo(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}
59 void PPCSubtarget::initializeEnvironment() {
61 DarwinDirective = PPC::DIR_NONE;
63 Has64BitSupport = false;
92 DeprecatedMFTB = false;
93 DeprecatedDST = false;
94 HasLazyResolverStubs = false;
96 HasInvariantFunctionDescriptors = false;
97 IsQPXStackUnaligned = false;
100 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
101 // Determine default and user specified characteristics
102 std::string CPUName = CPU;
103 if (CPUName.empty()) {
104 // If cross-compiling with -march=ppc64le without -mcpu
105 if (TargetTriple.getArch() == Triple::ppc64le)
110 #if (defined(__APPLE__) || defined(__linux__)) && \
111 (defined(__ppc__) || defined(__powerpc__))
112 if (CPUName == "generic")
113 CPUName = sys::getHostCPUName();
116 // Initialize scheduling itinerary for the specified CPU.
117 InstrItins = getInstrItineraryForCPU(CPUName);
119 // Parse features string.
120 ParseSubtargetFeatures(CPUName, FS);
122 // If the user requested use of 64-bit regs, but the cpu selected doesn't
123 // support it, ignore.
124 if (IsPPC64 && has64BitSupport())
127 // Set up darwin-specific properties.
129 HasLazyResolverStubs = true;
131 // QPX requires a 32-byte aligned stack. Note that we need to do this if
132 // we're compiling for a BG/Q system regardless of whether or not QPX
133 // is enabled because external functions will assume this alignment.
134 IsQPXStackUnaligned = QPXStackUnaligned;
135 StackAlignment = getPlatformStackAlignment();
137 // Determine endianness.
138 // FIXME: Part of the TargetMachine.
139 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
142 /// hasLazyResolverStub - Return true if accesses to the specified global have
143 /// to go through a dyld lazy resolution stub. This means that an extra load
144 /// is required to get the address of the global.
145 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
146 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
147 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
149 bool isDecl = GV->isDeclaration();
150 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
152 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
153 GV->hasCommonLinkage() || isDecl;
156 // Embedded cores need aggressive scheduling (and some others also benefit).
157 static bool needsAggressiveScheduling(unsigned Directive) {
159 default: return false;
162 case PPC::DIR_E500mc:
170 bool PPCSubtarget::enableMachineScheduler() const {
171 // Enable MI scheduling for the embedded cores.
172 // FIXME: Enable this for all cores (some additional modeling
173 // may be necessary).
174 return needsAggressiveScheduling(DarwinDirective);
177 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
178 bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
180 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
181 return TargetSubtargetInfo::ANTIDEP_ALL;
184 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
185 CriticalPathRCs.clear();
186 CriticalPathRCs.push_back(isPPC64() ?
187 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
190 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
193 unsigned NumRegionInstrs) const {
194 if (needsAggressiveScheduling(DarwinDirective)) {
195 Policy.OnlyTopDown = false;
196 Policy.OnlyBottomUp = false;
199 // Spilling is generally expensive on all PPC cores, so always enable
200 // register-pressure tracking.
201 Policy.ShouldTrackPressure = true;
204 bool PPCSubtarget::useAA() const {
205 // Use AA during code generation for the embedded cores.
206 return needsAggressiveScheduling(DarwinDirective);
209 bool PPCSubtarget::enableSubRegLiveness() const {
210 return UseSubRegLiveness;
213 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
214 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }