1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/IR/GlobalValue.h"
18 #include "llvm/Support/Host.h"
19 #include "llvm/Support/TargetRegistry.h"
20 #include "llvm/Target/TargetMachine.h"
23 #define GET_SUBTARGETINFO_TARGET_DESC
24 #define GET_SUBTARGETINFO_CTOR
25 #include "PPCGenSubtargetInfo.inc"
29 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
30 const std::string &FS, bool is64Bit)
31 : PPCGenSubtargetInfo(TT, CPU, FS)
33 , DarwinDirective(PPC::DIR_NONE)
35 , Has64BitSupport(false)
44 , HasLazyResolverStubs(false)
45 , IsJITCodeModel(false)
48 // Determine default and user specified characteristics
49 std::string CPUName = CPU;
52 #if (defined(__APPLE__) || defined(__linux__)) && \
53 (defined(__ppc__) || defined(__powerpc__))
54 if (CPUName == "generic")
55 CPUName = sys::getHostCPUName();
58 // Initialize scheduling itinerary for the specified CPU.
59 InstrItins = getInstrItineraryForCPU(CPUName);
61 // Make sure 64-bit features are available when CPUname is generic
62 std::string FullFS = FS;
64 // If we are generating code for ppc64, verify that options make sense.
66 Has64BitSupport = true;
67 // Silently force 64-bit register use on ppc64.
70 FullFS = "+64bit," + FullFS;
75 // Parse features string.
76 ParseSubtargetFeatures(CPUName, FullFS);
78 // If the user requested use of 64-bit regs, but the cpu selected doesn't
79 // support it, ignore.
80 if (use64BitRegs() && !has64BitSupport())
83 // Set up darwin-specific properties.
85 HasLazyResolverStubs = true;
88 /// SetJITMode - This is called to inform the subtarget info that we are
89 /// producing code for the JIT.
90 void PPCSubtarget::SetJITMode() {
91 // JIT mode doesn't want lazy resolver stubs, it knows exactly where
92 // everything is. This matters for PPC64, which codegens in PIC mode without
94 HasLazyResolverStubs = false;
96 // Calls to external functions need to use indirect calls
97 IsJITCodeModel = true;
101 /// hasLazyResolverStub - Return true if accesses to the specified global have
102 /// to go through a dyld lazy resolution stub. This means that an extra load
103 /// is required to get the address of the global.
104 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
105 const TargetMachine &TM) const {
106 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
107 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
109 // If symbol visibility is hidden, the extra load is not needed if
110 // the symbol is definitely defined in the current translation unit.
111 bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
112 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
114 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
115 GV->hasCommonLinkage() || isDecl;
118 bool PPCSubtarget::enablePostRAScheduler(
119 CodeGenOpt::Level OptLevel,
120 TargetSubtargetInfo::AntiDepBreakMode& Mode,
121 RegClassVector& CriticalPathRCs) const {
122 // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here,
123 // but we can't because we can't reassign the cr registers. There is a
124 // dependence between the cr register and the RLWINM instruction used
125 // to extract its value which the anti-dependency breaker can't currently
126 // see. Maybe we should make a late-expanded pseudo to encode this dependency.
127 // (the relevant code is in PPCDAGToDAGISel::SelectSETCC)
129 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
131 CriticalPathRCs.clear();
134 CriticalPathRCs.push_back(&PPC::G8RCRegClass);
136 CriticalPathRCs.push_back(&PPC::GPRCRegClass);
138 CriticalPathRCs.push_back(&PPC::F8RCRegClass);
139 CriticalPathRCs.push_back(&PPC::VRRCRegClass);
141 return OptLevel >= CodeGenOpt::Default;