1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
17 #include "PPCFrameLowering.h"
18 #include "PPCISelLowering.h"
19 #include "PPCInstrInfo.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/IR/DataLayout.h"
22 #include "llvm/MC/MCInstrItineraries.h"
23 #include "llvm/Target/TargetSelectionDAGInfo.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "PPCGenSubtargetInfo.inc"
30 // GCC #defines PPC on Linux but we use it as our namespace name
37 // -m directive values.
66 class PPCSubtarget : public PPCGenSubtargetInfo {
68 /// TargetTriple - What processor and OS we're targeting.
71 /// stackAlignment - The minimum alignment known to hold of the stack frame on
72 /// entry to the function and which must be maintained by every function.
73 unsigned StackAlignment;
75 /// Selected instruction itineraries (one entry per itinerary class.)
76 InstrItineraryData InstrItins;
78 /// Which cpu directive was used.
79 unsigned DarwinDirective;
81 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
96 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
115 bool HasLazyResolverStubs;
118 bool HasInvariantFunctionDescriptors;
119 bool HasPartwordAtomics;
123 /// When targeting QPX running a stock PPC64 Linux kernel where the stack
124 /// alignment has not been changed, we need to keep the 16-byte alignment
126 bool IsQPXStackUnaligned;
128 const PPCTargetMachine &TM;
129 PPCFrameLowering FrameLowering;
130 PPCInstrInfo InstrInfo;
131 PPCTargetLowering TLInfo;
132 TargetSelectionDAGInfo TSInfo;
135 /// This constructor initializes the data members to match that
136 /// of the specified triple.
138 PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
139 const PPCTargetMachine &TM);
141 /// ParseSubtargetFeatures - Parses features string setting specified
142 /// subtarget options. Definition of function is auto generated by tblgen.
143 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
145 /// getStackAlignment - Returns the minimum alignment known to hold of the
146 /// stack frame on entry to the function and which must be maintained by every
147 /// function for this subtarget.
148 unsigned getStackAlignment() const { return StackAlignment; }
150 /// getDarwinDirective - Returns the -m directive specified for the cpu.
152 unsigned getDarwinDirective() const { return DarwinDirective; }
154 /// getInstrItins - Return the instruction itineraries based on subtarget
156 const InstrItineraryData *getInstrItineraryData() const override {
160 const PPCFrameLowering *getFrameLowering() const override {
161 return &FrameLowering;
163 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
164 const PPCTargetLowering *getTargetLowering() const override {
167 const TargetSelectionDAGInfo *getSelectionDAGInfo() const override {
170 const PPCRegisterInfo *getRegisterInfo() const override {
171 return &getInstrInfo()->getRegisterInfo();
173 const PPCTargetMachine &getTargetMachine() const { return TM; }
175 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
176 /// so that we can use initializer lists for subtarget initialization.
177 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
180 void initializeEnvironment();
181 void initSubtargetFeatures(StringRef CPU, StringRef FS);
184 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
186 bool isPPC64() const;
188 /// has64BitSupport - Return true if the selected CPU supports 64-bit
189 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
190 bool has64BitSupport() const { return Has64BitSupport; }
192 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
193 /// registers in 32-bit mode when possible. This can only true if
194 /// has64BitSupport() returns true.
195 bool use64BitRegs() const { return Use64BitRegs; }
197 /// useCRBits - Return true if we should store and manipulate i1 values in
198 /// the individual condition register bits.
199 bool useCRBits() const { return UseCRBits; }
201 /// hasLazyResolverStub - Return true if accesses to the specified global have
202 /// to go through a dyld lazy resolution stub. This means that an extra load
203 /// is required to get the address of the global.
204 bool hasLazyResolverStub(const GlobalValue *GV) const;
206 // isLittleEndian - True if generating little-endian code
207 bool isLittleEndian() const { return IsLittleEndian; }
209 // Specific obvious features.
210 bool hasFCPSGN() const { return HasFCPSGN; }
211 bool hasFSQRT() const { return HasFSQRT; }
212 bool hasFRE() const { return HasFRE; }
213 bool hasFRES() const { return HasFRES; }
214 bool hasFRSQRTE() const { return HasFRSQRTE; }
215 bool hasFRSQRTES() const { return HasFRSQRTES; }
216 bool hasRecipPrec() const { return HasRecipPrec; }
217 bool hasSTFIWX() const { return HasSTFIWX; }
218 bool hasLFIWAX() const { return HasLFIWAX; }
219 bool hasFPRND() const { return HasFPRND; }
220 bool hasFPCVT() const { return HasFPCVT; }
221 bool hasAltivec() const { return HasAltivec; }
222 bool hasSPE() const { return HasSPE; }
223 bool hasQPX() const { return HasQPX; }
224 bool hasVSX() const { return HasVSX; }
225 bool hasP8Vector() const { return HasP8Vector; }
226 bool hasP8Altivec() const { return HasP8Altivec; }
227 bool hasP8Crypto() const { return HasP8Crypto; }
228 bool hasMFOCRF() const { return HasMFOCRF; }
229 bool hasISEL() const { return HasISEL; }
230 bool hasPOPCNTD() const { return HasPOPCNTD; }
231 bool hasBPERMD() const { return HasBPERMD; }
232 bool hasExtDiv() const { return HasExtDiv; }
233 bool hasCMPB() const { return HasCMPB; }
234 bool hasLDBRX() const { return HasLDBRX; }
235 bool isBookE() const { return IsBookE; }
236 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
237 bool isPPC4xx() const { return IsPPC4xx; }
238 bool isPPC6xx() const { return IsPPC6xx; }
239 bool isE500() const { return IsE500; }
240 bool isFeatureMFTB() const { return FeatureMFTB; }
241 bool isDeprecatedDST() const { return DeprecatedDST; }
242 bool hasICBT() const { return HasICBT; }
243 bool hasInvariantFunctionDescriptors() const {
244 return HasInvariantFunctionDescriptors;
246 bool hasPartwordAtomics() const { return HasPartwordAtomics; }
247 bool hasDirectMove() const { return HasDirectMove; }
249 bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
250 unsigned getPlatformStackAlignment() const {
251 if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
256 bool hasHTM() const { return HasHTM; }
258 const Triple &getTargetTriple() const { return TargetTriple; }
260 /// isDarwin - True if this is any darwin platform.
261 bool isDarwin() const { return TargetTriple.isMacOSX(); }
262 /// isBGQ - True if this is a BG/Q platform.
263 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
265 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
266 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
268 bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
269 bool isSVR4ABI() const { return !isDarwinABI(); }
270 bool isELFv2ABI() const;
272 bool enableEarlyIfConversion() const override { return hasISEL(); }
274 // Scheduling customization.
275 bool enableMachineScheduler() const override;
276 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
277 bool enablePostRAScheduler() const override;
278 AntiDepBreakMode getAntiDepBreakMode() const override;
279 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
281 void overrideSchedPolicy(MachineSchedPolicy &Policy,
284 unsigned NumRegionInstrs) const override;
285 bool useAA() const override;
287 bool enableSubRegLiveness() const override;
289 } // End llvm namespace