1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef POWERPCSUBTARGET_H
15 #define POWERPCSUBTARGET_H
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "PPCISelLowering.h"
20 #include "PPCJITInfo.h"
21 #include "PPCSelectionDAGInfo.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/MC/MCInstrItineraries.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
28 #define GET_SUBTARGETINFO_HEADER
29 #include "PPCGenSubtargetInfo.inc"
31 // GCC #defines PPC on Linux but we use it as our namespace name
38 // -m directive values.
66 class PPCSubtarget : public PPCGenSubtargetInfo {
68 /// stackAlignment - The minimum alignment known to hold of the stack frame on
69 /// entry to the function and which must be maintained by every function.
70 unsigned StackAlignment;
72 /// Selected instruction itineraries (one entry per itinerary class.)
73 InstrItineraryData InstrItins;
75 /// Which cpu directive was used.
76 unsigned DarwinDirective;
78 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
89 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
101 bool HasLazyResolverStubs;
105 /// TargetTriple - What processor and OS we're targeting.
108 /// OptLevel - What default optimization level we're emitting code for.
109 CodeGenOpt::Level OptLevel;
111 PPCFrameLowering FrameLowering;
113 PPCInstrInfo InstrInfo;
115 PPCTargetLowering TLInfo;
116 PPCSelectionDAGInfo TSInfo;
119 /// This constructor initializes the data members to match that
120 /// of the specified triple.
122 PPCSubtarget(const std::string &TT, const std::string &CPU,
123 const std::string &FS, PPCTargetMachine &TM, bool is64Bit,
124 CodeGenOpt::Level OptLevel);
126 /// ParseSubtargetFeatures - Parses features string setting specified
127 /// subtarget options. Definition of function is auto generated by tblgen.
128 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
130 /// SetJITMode - This is called to inform the subtarget info that we are
131 /// producing code for the JIT.
134 /// getStackAlignment - Returns the minimum alignment known to hold of the
135 /// stack frame on entry to the function and which must be maintained by every
136 /// function for this subtarget.
137 unsigned getStackAlignment() const { return StackAlignment; }
139 /// getDarwinDirective - Returns the -m directive specified for the cpu.
141 unsigned getDarwinDirective() const { return DarwinDirective; }
143 /// getInstrItins - Return the instruction itineraries based on subtarget
145 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
147 const PPCFrameLowering *getFrameLowering() const { return &FrameLowering; }
148 const DataLayout *getDataLayout() const { return &DL; }
149 const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
150 PPCJITInfo *getJITInfo() { return &JITInfo; }
151 const PPCTargetLowering *getTargetLowering() const { return &TLInfo; }
152 const PPCSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
154 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
155 /// so that we can use initializer lists for subtarget initialization.
156 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
158 /// \brief Reset the features for the PowerPC target.
159 void resetSubtargetFeatures(const MachineFunction *MF) override;
161 void initializeEnvironment();
162 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
165 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
167 bool isPPC64() const { return IsPPC64; }
169 /// has64BitSupport - Return true if the selected CPU supports 64-bit
170 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
171 bool has64BitSupport() const { return Has64BitSupport; }
173 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
174 /// registers in 32-bit mode when possible. This can only true if
175 /// has64BitSupport() returns true.
176 bool use64BitRegs() const { return Use64BitRegs; }
178 /// useCRBits - Return true if we should store and manipulate i1 values in
179 /// the individual condition register bits.
180 bool useCRBits() const { return UseCRBits; }
182 /// hasLazyResolverStub - Return true if accesses to the specified global have
183 /// to go through a dyld lazy resolution stub. This means that an extra load
184 /// is required to get the address of the global.
185 bool hasLazyResolverStub(const GlobalValue *GV,
186 const TargetMachine &TM) const;
188 // isJITCodeModel - True if we're generating code for the JIT
189 bool isJITCodeModel() const { return IsJITCodeModel; }
191 // isLittleEndian - True if generating little-endian code
192 bool isLittleEndian() const { return IsLittleEndian; }
194 // Specific obvious features.
195 bool hasFCPSGN() const { return HasFCPSGN; }
196 bool hasFSQRT() const { return HasFSQRT; }
197 bool hasFRE() const { return HasFRE; }
198 bool hasFRES() const { return HasFRES; }
199 bool hasFRSQRTE() const { return HasFRSQRTE; }
200 bool hasFRSQRTES() const { return HasFRSQRTES; }
201 bool hasRecipPrec() const { return HasRecipPrec; }
202 bool hasSTFIWX() const { return HasSTFIWX; }
203 bool hasLFIWAX() const { return HasLFIWAX; }
204 bool hasFPRND() const { return HasFPRND; }
205 bool hasFPCVT() const { return HasFPCVT; }
206 bool hasAltivec() const { return HasAltivec; }
207 bool hasQPX() const { return HasQPX; }
208 bool hasVSX() const { return HasVSX; }
209 bool hasMFOCRF() const { return HasMFOCRF; }
210 bool hasISEL() const { return HasISEL; }
211 bool hasPOPCNTD() const { return HasPOPCNTD; }
212 bool hasLDBRX() const { return HasLDBRX; }
213 bool isBookE() const { return IsBookE; }
214 bool isDeprecatedMFTB() const { return DeprecatedMFTB; }
215 bool isDeprecatedDST() const { return DeprecatedDST; }
217 const Triple &getTargetTriple() const { return TargetTriple; }
219 /// isDarwin - True if this is any darwin platform.
220 bool isDarwin() const { return TargetTriple.isMacOSX(); }
221 /// isBGQ - True if this is a BG/Q platform.
222 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
224 bool isDarwinABI() const { return isDarwin(); }
225 bool isSVR4ABI() const { return !isDarwin(); }
227 /// enablePostRAScheduler - True at 'More' optimization.
228 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
229 TargetSubtargetInfo::AntiDepBreakMode& Mode,
230 RegClassVector& CriticalPathRCs) const override;
232 bool enableEarlyIfConversion() const override { return hasISEL(); }
234 // Scheduling customization.
235 bool enableMachineScheduler() const override;
236 void overrideSchedPolicy(MachineSchedPolicy &Policy,
239 unsigned NumRegionInstrs) const override;
240 bool useAA() const override;
242 } // End llvm namespace