1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
17 #include "PPCFrameLowering.h"
18 #include "PPCISelLowering.h"
19 #include "PPCInstrInfo.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/IR/DataLayout.h"
22 #include "llvm/MC/MCInstrItineraries.h"
23 #include "llvm/Target/TargetSelectionDAGInfo.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "PPCGenSubtargetInfo.inc"
30 // GCC #defines PPC on Linux but we use it as our namespace name
37 // -m directive values.
66 class PPCSubtarget : public PPCGenSubtargetInfo {
68 /// TargetTriple - What processor and OS we're targeting.
71 /// stackAlignment - The minimum alignment known to hold of the stack frame on
72 /// entry to the function and which must be maintained by every function.
73 unsigned StackAlignment;
75 /// Selected instruction itineraries (one entry per itinerary class.)
76 InstrItineraryData InstrItins;
78 /// Which cpu directive was used.
79 unsigned DarwinDirective;
81 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
97 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
116 bool HasLazyResolverStubs;
119 bool HasInvariantFunctionDescriptors;
120 bool HasPartwordAtomics;
126 /// When targeting QPX running a stock PPC64 Linux kernel where the stack
127 /// alignment has not been changed, we need to keep the 16-byte alignment
129 bool IsQPXStackUnaligned;
131 const PPCTargetMachine &TM;
132 PPCFrameLowering FrameLowering;
133 PPCInstrInfo InstrInfo;
134 PPCTargetLowering TLInfo;
135 TargetSelectionDAGInfo TSInfo;
138 /// This constructor initializes the data members to match that
139 /// of the specified triple.
141 PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
142 const PPCTargetMachine &TM);
144 /// ParseSubtargetFeatures - Parses features string setting specified
145 /// subtarget options. Definition of function is auto generated by tblgen.
146 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
148 /// getStackAlignment - Returns the minimum alignment known to hold of the
149 /// stack frame on entry to the function and which must be maintained by every
150 /// function for this subtarget.
151 unsigned getStackAlignment() const { return StackAlignment; }
153 /// getDarwinDirective - Returns the -m directive specified for the cpu.
155 unsigned getDarwinDirective() const { return DarwinDirective; }
157 /// getInstrItins - Return the instruction itineraries based on subtarget
159 const InstrItineraryData *getInstrItineraryData() const override {
163 const PPCFrameLowering *getFrameLowering() const override {
164 return &FrameLowering;
166 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
167 const PPCTargetLowering *getTargetLowering() const override {
170 const TargetSelectionDAGInfo *getSelectionDAGInfo() const override {
173 const PPCRegisterInfo *getRegisterInfo() const override {
174 return &getInstrInfo()->getRegisterInfo();
176 const PPCTargetMachine &getTargetMachine() const { return TM; }
178 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
179 /// so that we can use initializer lists for subtarget initialization.
180 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
183 void initializeEnvironment();
184 void initSubtargetFeatures(StringRef CPU, StringRef FS);
187 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
189 bool isPPC64() const;
191 /// has64BitSupport - Return true if the selected CPU supports 64-bit
192 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
193 bool has64BitSupport() const { return Has64BitSupport; }
194 // useSoftFloat - Return true if soft-float option is turned on.
195 bool useSoftFloat() const { return UseSoftFloat; }
197 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
198 /// registers in 32-bit mode when possible. This can only true if
199 /// has64BitSupport() returns true.
200 bool use64BitRegs() const { return Use64BitRegs; }
202 /// useCRBits - Return true if we should store and manipulate i1 values in
203 /// the individual condition register bits.
204 bool useCRBits() const { return UseCRBits; }
206 /// hasLazyResolverStub - Return true if accesses to the specified global have
207 /// to go through a dyld lazy resolution stub. This means that an extra load
208 /// is required to get the address of the global.
209 bool hasLazyResolverStub(const GlobalValue *GV) const;
211 // isLittleEndian - True if generating little-endian code
212 bool isLittleEndian() const { return IsLittleEndian; }
214 // Specific obvious features.
215 bool hasFCPSGN() const { return HasFCPSGN; }
216 bool hasFSQRT() const { return HasFSQRT; }
217 bool hasFRE() const { return HasFRE; }
218 bool hasFRES() const { return HasFRES; }
219 bool hasFRSQRTE() const { return HasFRSQRTE; }
220 bool hasFRSQRTES() const { return HasFRSQRTES; }
221 bool hasRecipPrec() const { return HasRecipPrec; }
222 bool hasSTFIWX() const { return HasSTFIWX; }
223 bool hasLFIWAX() const { return HasLFIWAX; }
224 bool hasFPRND() const { return HasFPRND; }
225 bool hasFPCVT() const { return HasFPCVT; }
226 bool hasAltivec() const { return HasAltivec; }
227 bool hasSPE() const { return HasSPE; }
228 bool hasQPX() const { return HasQPX; }
229 bool hasVSX() const { return HasVSX; }
230 bool hasP8Vector() const { return HasP8Vector; }
231 bool hasP8Altivec() const { return HasP8Altivec; }
232 bool hasP8Crypto() const { return HasP8Crypto; }
233 bool hasMFOCRF() const { return HasMFOCRF; }
234 bool hasISEL() const { return HasISEL; }
235 bool hasPOPCNTD() const { return HasPOPCNTD; }
236 bool hasBPERMD() const { return HasBPERMD; }
237 bool hasExtDiv() const { return HasExtDiv; }
238 bool hasCMPB() const { return HasCMPB; }
239 bool hasLDBRX() const { return HasLDBRX; }
240 bool isBookE() const { return IsBookE; }
241 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
242 bool isPPC4xx() const { return IsPPC4xx; }
243 bool isPPC6xx() const { return IsPPC6xx; }
244 bool isE500() const { return IsE500; }
245 bool isFeatureMFTB() const { return FeatureMFTB; }
246 bool isDeprecatedDST() const { return DeprecatedDST; }
247 bool hasICBT() const { return HasICBT; }
248 bool hasInvariantFunctionDescriptors() const {
249 return HasInvariantFunctionDescriptors;
251 bool hasPartwordAtomics() const { return HasPartwordAtomics; }
252 bool hasDirectMove() const { return HasDirectMove; }
254 bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
255 unsigned getPlatformStackAlignment() const {
256 if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
261 bool hasHTM() const { return HasHTM; }
262 bool hasFusion() const { return HasFusion; }
263 bool hasFloat128() const { return HasFloat128; }
265 const Triple &getTargetTriple() const { return TargetTriple; }
267 /// isDarwin - True if this is any darwin platform.
268 bool isDarwin() const { return TargetTriple.isMacOSX(); }
269 /// isBGQ - True if this is a BG/Q platform.
270 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
272 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
273 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
275 bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
276 bool isSVR4ABI() const { return !isDarwinABI(); }
277 bool isELFv2ABI() const;
279 bool enableEarlyIfConversion() const override { return hasISEL(); }
281 // Scheduling customization.
282 bool enableMachineScheduler() const override;
283 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
284 bool enablePostRAScheduler() const override;
285 AntiDepBreakMode getAntiDepBreakMode() const override;
286 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
288 void overrideSchedPolicy(MachineSchedPolicy &Policy,
291 unsigned NumRegionInstrs) const override;
292 bool useAA() const override;
294 bool enableSubRegLiveness() const override;
296 /// classifyGlobalReference - Classify a global variable reference for the
297 /// current subtarget accourding to how we should reference it.
298 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
300 } // End llvm namespace