1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
17 #include "PPCFrameLowering.h"
18 #include "PPCISelLowering.h"
19 #include "PPCInstrInfo.h"
20 #include "PPCSelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "PPCGenSubtargetInfo.inc"
30 // GCC #defines PPC on Linux but we use it as our namespace name
37 // -m directive values.
66 class PPCSubtarget : public PPCGenSubtargetInfo {
68 /// TargetTriple - What processor and OS we're targeting.
71 /// stackAlignment - The minimum alignment known to hold of the stack frame on
72 /// entry to the function and which must be maintained by every function.
73 unsigned StackAlignment;
75 /// Selected instruction itineraries (one entry per itinerary class.)
76 InstrItineraryData InstrItins;
78 /// Which cpu directive was used.
79 unsigned DarwinDirective;
81 /// Used by the ISel to turn in optimizations for POWER4-derived architectures
95 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
112 bool HasLazyResolverStubs;
115 bool HasInvariantFunctionDescriptors;
117 const PPCTargetMachine &TM;
118 PPCFrameLowering FrameLowering;
119 PPCInstrInfo InstrInfo;
120 PPCTargetLowering TLInfo;
121 PPCSelectionDAGInfo TSInfo;
124 /// This constructor initializes the data members to match that
125 /// of the specified triple.
127 PPCSubtarget(const std::string &TT, const std::string &CPU,
128 const std::string &FS, const PPCTargetMachine &TM);
130 /// ParseSubtargetFeatures - Parses features string setting specified
131 /// subtarget options. Definition of function is auto generated by tblgen.
132 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
134 /// getStackAlignment - Returns the minimum alignment known to hold of the
135 /// stack frame on entry to the function and which must be maintained by every
136 /// function for this subtarget.
137 unsigned getStackAlignment() const { return StackAlignment; }
139 /// getDarwinDirective - Returns the -m directive specified for the cpu.
141 unsigned getDarwinDirective() const { return DarwinDirective; }
143 /// getInstrItins - Return the instruction itineraries based on subtarget
145 const InstrItineraryData *getInstrItineraryData() const override {
149 const PPCFrameLowering *getFrameLowering() const override {
150 return &FrameLowering;
152 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
153 const PPCTargetLowering *getTargetLowering() const override {
156 const PPCSelectionDAGInfo *getSelectionDAGInfo() const override {
159 const PPCRegisterInfo *getRegisterInfo() const override {
160 return &getInstrInfo()->getRegisterInfo();
162 const PPCTargetMachine &getTargetMachine() const { return TM; }
164 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
165 /// so that we can use initializer lists for subtarget initialization.
166 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
169 void initializeEnvironment();
170 void initSubtargetFeatures(StringRef CPU, StringRef FS);
173 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
175 bool isPPC64() const;
177 /// has64BitSupport - Return true if the selected CPU supports 64-bit
178 /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
179 bool has64BitSupport() const { return Has64BitSupport; }
181 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
182 /// registers in 32-bit mode when possible. This can only true if
183 /// has64BitSupport() returns true.
184 bool use64BitRegs() const { return Use64BitRegs; }
186 /// useCRBits - Return true if we should store and manipulate i1 values in
187 /// the individual condition register bits.
188 bool useCRBits() const { return UseCRBits; }
190 /// hasLazyResolverStub - Return true if accesses to the specified global have
191 /// to go through a dyld lazy resolution stub. This means that an extra load
192 /// is required to get the address of the global.
193 bool hasLazyResolverStub(const GlobalValue *GV) const;
195 // isLittleEndian - True if generating little-endian code
196 bool isLittleEndian() const { return IsLittleEndian; }
198 // Specific obvious features.
199 bool hasFCPSGN() const { return HasFCPSGN; }
200 bool hasFSQRT() const { return HasFSQRT; }
201 bool hasFRE() const { return HasFRE; }
202 bool hasFRES() const { return HasFRES; }
203 bool hasFRSQRTE() const { return HasFRSQRTE; }
204 bool hasFRSQRTES() const { return HasFRSQRTES; }
205 bool hasRecipPrec() const { return HasRecipPrec; }
206 bool hasSTFIWX() const { return HasSTFIWX; }
207 bool hasLFIWAX() const { return HasLFIWAX; }
208 bool hasFPRND() const { return HasFPRND; }
209 bool hasFPCVT() const { return HasFPCVT; }
210 bool hasAltivec() const { return HasAltivec; }
211 bool hasSPE() const { return HasSPE; }
212 bool hasQPX() const { return HasQPX; }
213 bool hasVSX() const { return HasVSX; }
214 bool hasP8Vector() const { return HasP8Vector; }
215 bool hasP8Altivec() const { return HasP8Altivec; }
216 bool hasMFOCRF() const { return HasMFOCRF; }
217 bool hasISEL() const { return HasISEL; }
218 bool hasPOPCNTD() const { return HasPOPCNTD; }
219 bool hasCMPB() const { return HasCMPB; }
220 bool hasLDBRX() const { return HasLDBRX; }
221 bool isBookE() const { return IsBookE; }
222 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
223 bool isPPC4xx() const { return IsPPC4xx; }
224 bool isPPC6xx() const { return IsPPC6xx; }
225 bool isE500() const { return IsE500; }
226 bool isDeprecatedMFTB() const { return DeprecatedMFTB; }
227 bool isDeprecatedDST() const { return DeprecatedDST; }
228 bool hasICBT() const { return HasICBT; }
229 bool hasInvariantFunctionDescriptors() const {
230 return HasInvariantFunctionDescriptors;
233 const Triple &getTargetTriple() const { return TargetTriple; }
235 /// isDarwin - True if this is any darwin platform.
236 bool isDarwin() const { return TargetTriple.isMacOSX(); }
237 /// isBGQ - True if this is a BG/Q platform.
238 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
240 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
241 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
243 bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
244 bool isSVR4ABI() const { return !isDarwinABI(); }
245 bool isELFv2ABI() const;
247 bool enableEarlyIfConversion() const override { return hasISEL(); }
249 // Scheduling customization.
250 bool enableMachineScheduler() const override;
251 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
252 bool enablePostMachineScheduler() const override;
253 AntiDepBreakMode getAntiDepBreakMode() const override;
254 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
256 void overrideSchedPolicy(MachineSchedPolicy &Policy,
259 unsigned NumRegionInstrs) const override;
260 bool useAA() const override;
262 bool enableSubRegLiveness() const override;
264 } // End llvm namespace