1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31 cl::desc("Disable CTR loops for PPC"));
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35 cl::desc("Disable PPC loop preinc prep"));
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
42 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
43 cl::desc("Enable optimizations on complex GEPs"),
46 extern "C" void LLVMInitializePowerPCTarget() {
47 // Register the targets
48 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
49 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
50 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
53 /// Return the datalayout string of a subtarget.
54 static std::string getDataLayoutString(const Triple &T) {
55 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
58 // Most PPC* platforms are big endian, PPC64LE is little endian.
59 if (T.getArch() == Triple::ppc64le)
64 Ret += DataLayout::getManglingComponent(T);
66 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
68 if (!is64Bit || T.getOS() == Triple::Lv2)
71 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
72 // documentation are wrong; these are correct (i.e. "what gcc does").
73 if (is64Bit || !T.isOSDarwin())
78 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
87 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
88 std::string FullFS = FS;
89 Triple TargetTriple(TT);
91 // Make sure 64-bit features are available when CPUname is generic
92 if (TargetTriple.getArch() == Triple::ppc64 ||
93 TargetTriple.getArch() == Triple::ppc64le) {
95 FullFS = "+64bit," + FullFS;
100 if (OL >= CodeGenOpt::Default) {
102 FullFS = "+crbits," + FullFS;
107 if (OL != CodeGenOpt::None) {
109 FullFS = "+invariant-function-descriptors," + FullFS;
111 FullFS = "+invariant-function-descriptors";
117 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
118 // If it isn't a Mach-O file then it's going to be a linux ELF
121 return make_unique<TargetLoweringObjectFileMachO>();
123 return make_unique<PPC64LinuxTargetObjectFile>();
126 // The FeatureString here is a little subtle. We are modifying the feature string
127 // with what are (currently) non-function specific overrides as it goes into the
128 // LLVMTargetMachine constructor and then using the stored value in the
129 // Subtarget constructor below it.
130 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
131 StringRef FS, const TargetOptions &Options,
132 Reloc::Model RM, CodeModel::Model CM,
133 CodeGenOpt::Level OL)
134 : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
136 TLOF(createTLOF(Triple(getTargetTriple()))),
137 DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) {
141 PPCTargetMachine::~PPCTargetMachine() {}
143 void PPC32TargetMachine::anchor() { }
145 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
146 StringRef CPU, StringRef FS,
147 const TargetOptions &Options,
148 Reloc::Model RM, CodeModel::Model CM,
149 CodeGenOpt::Level OL)
150 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
153 void PPC64TargetMachine::anchor() { }
155 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
156 StringRef CPU, StringRef FS,
157 const TargetOptions &Options,
158 Reloc::Model RM, CodeModel::Model CM,
159 CodeGenOpt::Level OL)
160 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
164 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
165 Attribute CPUAttr = F.getFnAttribute("target-cpu");
166 Attribute FSAttr = F.getFnAttribute("target-features");
168 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
169 ? CPUAttr.getValueAsString().str()
171 std::string FS = !FSAttr.hasAttribute(Attribute::None)
172 ? FSAttr.getValueAsString().str()
175 auto &I = SubtargetMap[CPU + FS];
177 // This needs to be done before we create a new subtarget since any
178 // creation will depend on the TM and the code generation flags on the
179 // function that reside in TargetOptions.
180 resetTargetOptions(F);
181 I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
186 //===----------------------------------------------------------------------===//
187 // Pass Pipeline Configuration
188 //===----------------------------------------------------------------------===//
191 /// PPC Code Generator Pass Configuration Options.
192 class PPCPassConfig : public TargetPassConfig {
194 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
195 : TargetPassConfig(TM, PM) {}
197 PPCTargetMachine &getPPCTargetMachine() const {
198 return getTM<PPCTargetMachine>();
201 void addIRPasses() override;
202 bool addPreISel() override;
203 bool addILPOpts() override;
204 bool addInstSelector() override;
205 void addPreRegAlloc() override;
206 void addPreSched2() override;
207 void addPreEmitPass() override;
211 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
212 return new PPCPassConfig(this, PM);
215 void PPCPassConfig::addIRPasses() {
216 addPass(createAtomicExpandPass(&getPPCTargetMachine()));
218 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
219 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
220 // and lower a GEP with multiple indices to either arithmetic operations or
221 // multiple GEPs with single index.
222 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
223 // Call EarlyCSE pass to find and remove subexpressions in the lowered
225 addPass(createEarlyCSEPass());
226 // Do loop invariant code motion in case part of the lowered result is
228 addPass(createLICMPass());
231 TargetPassConfig::addIRPasses();
234 bool PPCPassConfig::addPreISel() {
235 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
236 addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
238 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
239 addPass(createPPCCTRLoops(getPPCTargetMachine()));
244 bool PPCPassConfig::addILPOpts() {
245 addPass(&EarlyIfConverterID);
249 bool PPCPassConfig::addInstSelector() {
250 // Install an instruction selector.
251 addPass(createPPCISelDag(getPPCTargetMachine()));
254 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
255 addPass(createPPCCTRLoopsVerify());
258 addPass(createPPCVSXCopyPass());
262 void PPCPassConfig::addPreRegAlloc() {
263 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
264 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
266 if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
267 addPass(createPPCTLSDynamicCallPass());
270 void PPCPassConfig::addPreSched2() {
271 if (getOptLevel() != CodeGenOpt::None)
272 addPass(&IfConverterID);
275 void PPCPassConfig::addPreEmitPass() {
276 if (getOptLevel() != CodeGenOpt::None)
277 addPass(createPPCEarlyReturnPass(), false);
278 // Must run branch selection immediately preceding the asm printer.
279 addPass(createPPCBranchSelectionPass(), false);
282 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
283 return TargetIRAnalysis(
284 [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });