1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
15 #include "PPCTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/Target/TargetOptions.h"
19 #include "llvm/Target/TargetRegistry.h"
20 #include "llvm/Support/FormattedStream.h"
23 // This is duplicated code. Refactor this.
24 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
25 MCContext &Ctx, TargetAsmBackend &TAB,
27 MCCodeEmitter *Emitter,
30 if (Triple(TT).isOSDarwin())
31 return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
36 extern "C" void LLVMInitializePowerPCTarget() {
37 // Register the targets
38 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
39 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
41 // Register the MC Code Emitter
42 TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
43 TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
46 // Register the asm backend.
47 TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend);
48 TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend);
50 // Register the object streamer.
51 TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer);
52 TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
55 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
56 StringRef CPU, StringRef FS,
57 Reloc::Model RM, bool is64Bit)
58 : LLVMTargetMachine(T, TT, CPU, FS, RM),
59 Subtarget(TT, CPU, FS, is64Bit),
60 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
61 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
62 TLInfo(*this), TSInfo(*this),
63 InstrItins(Subtarget.getInstrItineraryData()) {
66 /// Override this for PowerPC. Tail merging happily breaks up instruction issue
67 /// groups, which typically degrades performance.
68 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
70 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
72 StringRef FS, Reloc::Model RM)
73 : PPCTargetMachine(T, TT, CPU, FS, RM, false) {
77 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
79 StringRef FS, Reloc::Model RM)
80 : PPCTargetMachine(T, TT, CPU, FS, RM, true) {
84 //===----------------------------------------------------------------------===//
85 // Pass Pipeline Configuration
86 //===----------------------------------------------------------------------===//
88 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
89 CodeGenOpt::Level OptLevel) {
90 // Install an instruction selector.
91 PM.add(createPPCISelDag(*this));
95 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
96 CodeGenOpt::Level OptLevel) {
97 // Must run branch selection immediately preceding the asm printer.
98 PM.add(createPPCBranchSelectionPass());
102 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
103 CodeGenOpt::Level OptLevel,
104 JITCodeEmitter &JCE) {
105 // FIXME: This should be moved to TargetJITInfo!!
106 if (Subtarget.isPPC64())
107 // Temporary workaround for the inability of PPC64 JIT to handle jump
109 DisableJumpTables = true;
111 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
113 Subtarget.SetJITMode();
115 // Machine code emitter pass for PowerPC.
116 PM.add(createPPCJITCodeEmitterPass(*this, JCE));