1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
15 #include "PPCMCAsmInfo.h"
16 #include "PPCTargetMachine.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Support/FormattedStream.h"
24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
26 bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
27 if (TheTriple.getOS() == Triple::Darwin)
28 return new PPCMCAsmInfoDarwin(isPPC64);
29 return new PPCLinuxMCAsmInfo(isPPC64);
33 // This is duplicated code. Refactor this.
34 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
35 MCContext &Ctx, TargetAsmBackend &TAB,
37 MCCodeEmitter *Emitter,
40 switch (Triple(TT).getOS()) {
42 return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
48 extern "C" void LLVMInitializePowerPCTarget() {
49 // Register the targets
50 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
51 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
53 RegisterAsmInfoFn C(ThePPC32Target, createMCAsmInfo);
54 RegisterAsmInfoFn D(ThePPC64Target, createMCAsmInfo);
56 // Register the MC Code Emitter
57 TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
58 TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
61 // Register the asm backend.
62 TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend);
63 TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend);
65 // Register the object streamer.
66 TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer);
67 TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
71 PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
72 const std::string &FS, bool is64Bit)
73 : LLVMTargetMachine(T, TT),
74 Subtarget(TT, FS, is64Bit),
75 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
76 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
77 TLInfo(*this), TSInfo(*this),
78 InstrItins(Subtarget.getInstrItineraryData()) {
80 if (getRelocationModel() == Reloc::Default) {
81 if (Subtarget.isDarwin())
82 setRelocationModel(Reloc::DynamicNoPIC);
84 setRelocationModel(Reloc::Static);
88 /// Override this for PowerPC. Tail merging happily breaks up instruction issue
89 /// groups, which typically degrades performance.
90 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
92 PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT,
93 const std::string &FS)
94 : PPCTargetMachine(T, TT, FS, false) {
98 PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT,
99 const std::string &FS)
100 : PPCTargetMachine(T, TT, FS, true) {
104 //===----------------------------------------------------------------------===//
105 // Pass Pipeline Configuration
106 //===----------------------------------------------------------------------===//
108 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
109 CodeGenOpt::Level OptLevel) {
110 // Install an instruction selector.
111 PM.add(createPPCISelDag(*this));
115 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
116 CodeGenOpt::Level OptLevel) {
117 // Must run branch selection immediately preceding the asm printer.
118 PM.add(createPPCBranchSelectionPass());
122 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
123 CodeGenOpt::Level OptLevel,
124 JITCodeEmitter &JCE) {
125 // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
126 // FIXME: This should be moved to TargetJITInfo!!
127 if (Subtarget.isPPC64()) {
128 // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
129 // instructions to materialize arbitrary global variable + function +
130 // constant pool addresses.
131 setRelocationModel(Reloc::PIC_);
132 // Temporary workaround for the inability of PPC64 JIT to handle jump
134 DisableJumpTables = true;
136 setRelocationModel(Reloc::Static);
139 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
141 Subtarget.SetJITMode();
143 // Machine code emitter pass for PowerPC.
144 PM.add(createPPCJITCodeEmitterPass(*this, JCE));