1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
29 extern "C" void LLVMInitializePowerPCTarget() {
30 // Register the targets
31 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
36 /// Return the datalayout string of a subtarget.
37 static std::string getDataLayoutString(const PPCSubtarget &ST) {
38 const Triple &T = ST.getTargetTriple();
41 std::string Ret = "E";
43 Ret += DataLayout::getManglingComponent(T);
45 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
47 if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
50 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
51 // documentation are wrong; these are correct (i.e. "what gcc does").
52 if (ST.isPPC64() || ST.isSVR4ABI())
57 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
66 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
67 StringRef CPU, StringRef FS,
68 const TargetOptions &Options,
69 Reloc::Model RM, CodeModel::Model CM,
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73 Subtarget(TT, CPU, FS, is64Bit),
74 DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
75 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
76 TLInfo(*this), TSInfo(*this),
77 InstrItins(Subtarget.getInstrItineraryData()) {
79 // The binutils for the BG/P are too old for CFI.
80 if (Subtarget.isBGP())
85 void PPC32TargetMachine::anchor() { }
87 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
88 StringRef CPU, StringRef FS,
89 const TargetOptions &Options,
90 Reloc::Model RM, CodeModel::Model CM,
92 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
95 void PPC64TargetMachine::anchor() { }
97 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
98 StringRef CPU, StringRef FS,
99 const TargetOptions &Options,
100 Reloc::Model RM, CodeModel::Model CM,
101 CodeGenOpt::Level OL)
102 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
106 //===----------------------------------------------------------------------===//
107 // Pass Pipeline Configuration
108 //===----------------------------------------------------------------------===//
111 /// PPC Code Generator Pass Configuration Options.
112 class PPCPassConfig : public TargetPassConfig {
114 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
115 : TargetPassConfig(TM, PM) {}
117 PPCTargetMachine &getPPCTargetMachine() const {
118 return getTM<PPCTargetMachine>();
121 const PPCSubtarget &getPPCSubtarget() const {
122 return *getPPCTargetMachine().getSubtargetImpl();
125 virtual bool addPreISel();
126 virtual bool addILPOpts();
127 virtual bool addInstSelector();
128 virtual bool addPreSched2();
129 virtual bool addPreEmitPass();
133 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
134 return new PPCPassConfig(this, PM);
137 bool PPCPassConfig::addPreISel() {
138 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
139 addPass(createPPCCTRLoops(getPPCTargetMachine()));
144 bool PPCPassConfig::addILPOpts() {
145 if (getPPCSubtarget().hasISEL()) {
146 addPass(&EarlyIfConverterID);
153 bool PPCPassConfig::addInstSelector() {
154 // Install an instruction selector.
155 addPass(createPPCISelDag(getPPCTargetMachine()));
158 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
159 addPass(createPPCCTRLoopsVerify());
165 bool PPCPassConfig::addPreSched2() {
166 if (getOptLevel() != CodeGenOpt::None)
167 addPass(&IfConverterID);
172 bool PPCPassConfig::addPreEmitPass() {
173 if (getOptLevel() != CodeGenOpt::None)
174 addPass(createPPCEarlyReturnPass());
175 // Must run branch selection immediately preceding the asm printer.
176 addPass(createPPCBranchSelectionPass());
180 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
181 JITCodeEmitter &JCE) {
182 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
184 Subtarget.SetJITMode();
186 // Machine code emitter pass for PowerPC.
187 PM.add(createPPCJITCodeEmitterPass(*this, JCE));
192 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
193 // Add first the target-independent BasicTTI pass, then our PPC pass. This
194 // allows the PPC pass to delegate to the target independent layer when
196 PM.add(createBasicTargetTransformInfoPass(this));
197 PM.add(createPPCTargetTransformInfoPass(this));