1 //===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "PowerPCTargetMachine.h"
15 #include "PowerPCFrameInfo.h"
16 #include "PPC32TargetMachine.h"
17 #include "PPC64TargetMachine.h"
18 #include "PPC32JITInfo.h"
19 #include "PPC64JITInfo.h"
20 #include "llvm/Module.h"
21 #include "llvm/PassManager.h"
22 #include "llvm/CodeGen/IntrinsicLowering.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Target/TargetMachineRegistry.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include "llvm/Support/CommandLine.h"
33 cl::opt<bool> AIX("aix",
34 cl::desc("Generate AIX/xcoff instead of Darwin/MachO"),
37 cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
38 cl::desc("Enable LSR for PPC (beta option!)"),
40 cl::opt<bool> EnablePatternISel("enable-ppc-pattern-isel", cl::Hidden,
41 cl::desc("Enable the pattern isel"));
45 const std::string PPC32ID = "PowerPC/32bit";
46 const std::string PPC64ID = "PowerPC/64bit";
48 // Register the targets
49 RegisterTarget<PPC32TargetMachine>
50 X("ppc32", " PowerPC 32-bit");
53 RegisterTarget<PPC64TargetMachine>
54 Y("ppc64", " PowerPC 64-bit (unimplemented)");
58 PowerPCTargetMachine::PowerPCTargetMachine(const std::string &name,
59 IntrinsicLowering *IL,
61 const PowerPCFrameInfo &TFI)
62 : TargetMachine(name, IL, TD), FrameInfo(TFI)
65 unsigned PPC32TargetMachine::getJITMatchQuality() {
66 #if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
73 /// addPassesToEmitAssembly - Add passes to the specified pass manager
74 /// to implement a static compiler for this target.
76 bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
78 bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(this));
81 PM.add(createLoopStrengthReducePass());
82 PM.add(createCFGSimplificationPass());
85 // FIXME: Implement efficient support for garbage collection intrinsics.
86 PM.add(createLowerGCPass());
88 // FIXME: Implement the invoke/unwind instructions!
89 PM.add(createLowerInvokePass());
91 // FIXME: Implement the switch instruction in the instruction selector!
92 PM.add(createLowerSwitchPass());
94 PM.add(createLowerConstantExpressionsPass());
96 // Make sure that no unreachable blocks are instruction selected.
97 PM.add(createUnreachableBlockEliminationPass());
100 PM.add(createPPC64ISelPattern(*this));
101 else if (EnablePatternISel)
102 PM.add(createPPC32ISelPattern(*this));
104 PM.add(createPPC32ISelSimple(*this));
106 if (PrintMachineCode)
107 PM.add(createMachineFunctionPrinterPass(&std::cerr));
109 PM.add(createRegisterAllocator());
111 if (PrintMachineCode)
112 PM.add(createMachineFunctionPrinterPass(&std::cerr));
114 PM.add(createPrologEpilogCodeInserter());
116 // Must run branch selection immediately preceding the asm printer
117 PM.add(createPPCBranchSelectionPass());
120 PM.add(createAIXAsmPrinter(Out, *this));
122 PM.add(createDarwinAsmPrinter(Out, *this));
124 PM.add(createMachineCodeDeleter());
128 void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
130 PM.add(createLoopStrengthReducePass());
131 PM.add(createCFGSimplificationPass());
134 // FIXME: Implement efficient support for garbage collection intrinsics.
135 PM.add(createLowerGCPass());
137 // FIXME: Implement the invoke/unwind instructions!
138 PM.add(createLowerInvokePass());
140 // FIXME: Implement the switch instruction in the instruction selector!
141 PM.add(createLowerSwitchPass());
143 PM.add(createLowerConstantExpressionsPass());
145 // Make sure that no unreachable blocks are instruction selected.
146 PM.add(createUnreachableBlockEliminationPass());
148 PM.add(createPPC32ISelSimple(TM));
149 PM.add(createRegisterAllocator());
150 PM.add(createPrologEpilogCodeInserter());
152 // Must run branch selection immediately preceding the asm printer
153 PM.add(createPPCBranchSelectionPass());
155 if (PrintMachineCode)
156 PM.add(createMachineFunctionPrinterPass(&std::cerr));
159 /// PowerPCTargetMachine ctor - Create an ILP32 architecture model
161 PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL)
162 : PowerPCTargetMachine(PPC32ID, IL,
163 TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
164 PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
166 /// PPC64TargetMachine ctor - Create a LP64 architecture model
168 PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL)
169 : PowerPCTargetMachine(PPC64ID, IL,
170 TargetData(PPC64ID,false,8,4,4,4,4,4,2,1,1),
171 PowerPCFrameInfo(*this, true)) {}
173 unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
174 // We strongly match "powerpc-*".
175 std::string TT = M.getTargetTriple();
176 if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
179 if (M.getEndianness() == Module::BigEndian &&
180 M.getPointerSize() == Module::Pointer32)
181 return 10; // Weak match
182 else if (M.getEndianness() != Module::AnyEndianness ||
183 M.getPointerSize() != Module::AnyPointerSize)
184 return 0; // Match for some other target
186 return getJITMatchQuality()/2;
189 unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
190 if (M.getEndianness() == Module::BigEndian &&
191 M.getPointerSize() == Module::Pointer64)
192 return 10; // Direct match
193 else if (M.getEndianness() != Module::AnyEndianness ||
194 M.getPointerSize() != Module::AnyPointerSize)
195 return 0; // Match for some other target
197 return getJITMatchQuality()/2;