1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
15 #include "PPCMCAsmInfo.h"
16 #include "PPCTargetMachine.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Support/FormattedStream.h"
24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
26 bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
27 if (TheTriple.getOS() == Triple::Darwin)
28 return new PPCMCAsmInfoDarwin(isPPC64);
29 return new PPCLinuxMCAsmInfo(isPPC64);
33 // This is duplicated code. Refactor this.
34 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
35 MCContext &Ctx, TargetAsmBackend &TAB,
37 MCCodeEmitter *Emitter,
39 switch (Triple(TT).getOS()) {
41 return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
47 extern "C" void LLVMInitializePowerPCTarget() {
48 // Register the targets
49 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
50 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
52 RegisterAsmInfoFn C(ThePPC32Target, createMCAsmInfo);
53 RegisterAsmInfoFn D(ThePPC64Target, createMCAsmInfo);
55 // Register the MC Code Emitter
56 TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
57 TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
60 // Register the asm backend.
61 TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend);
62 TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend);
64 // Register the object streamer.
65 TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer);
66 TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
70 PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
71 const std::string &FS, bool is64Bit)
72 : LLVMTargetMachine(T, TT),
73 Subtarget(TT, FS, is64Bit),
74 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
75 FrameInfo(Subtarget), JITInfo(*this, is64Bit),
76 TLInfo(*this), TSInfo(*this),
77 InstrItins(Subtarget.getInstrItineraryData()) {
79 if (getRelocationModel() == Reloc::Default) {
80 if (Subtarget.isDarwin())
81 setRelocationModel(Reloc::DynamicNoPIC);
83 setRelocationModel(Reloc::Static);
87 /// Override this for PowerPC. Tail merging happily breaks up instruction issue
88 /// groups, which typically degrades performance.
89 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
91 PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT,
92 const std::string &FS)
93 : PPCTargetMachine(T, TT, FS, false) {
97 PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT,
98 const std::string &FS)
99 : PPCTargetMachine(T, TT, FS, true) {
103 //===----------------------------------------------------------------------===//
104 // Pass Pipeline Configuration
105 //===----------------------------------------------------------------------===//
107 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
108 CodeGenOpt::Level OptLevel) {
109 // Install an instruction selector.
110 PM.add(createPPCISelDag(*this));
114 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
115 CodeGenOpt::Level OptLevel) {
116 // Must run branch selection immediately preceding the asm printer.
117 PM.add(createPPCBranchSelectionPass());
121 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
122 CodeGenOpt::Level OptLevel,
123 JITCodeEmitter &JCE) {
124 // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
125 // FIXME: This should be moved to TargetJITInfo!!
126 if (Subtarget.isPPC64()) {
127 // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
128 // instructions to materialize arbitrary global variable + function +
129 // constant pool addresses.
130 setRelocationModel(Reloc::PIC_);
131 // Temporary workaround for the inability of PPC64 JIT to handle jump
133 DisableJumpTables = true;
135 setRelocationModel(Reloc::Static);
138 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
140 Subtarget.SetJITMode();
142 // Machine code emitter pass for PowerPC.
143 PM.add(createPPCJITCodeEmitterPass(*this, JCE));