1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
30 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
31 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
33 extern "C" void LLVMInitializePowerPCTarget() {
34 // Register the targets
35 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
36 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
37 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
40 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
41 StringRef FS, const TargetOptions &Options,
42 Reloc::Model RM, CodeModel::Model CM,
43 CodeGenOpt::Level OL, bool is64Bit)
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, *this, is64Bit, OL) {
49 void PPC32TargetMachine::anchor() { }
51 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
52 StringRef CPU, StringRef FS,
53 const TargetOptions &Options,
54 Reloc::Model RM, CodeModel::Model CM,
56 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
59 void PPC64TargetMachine::anchor() { }
61 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
62 StringRef CPU, StringRef FS,
63 const TargetOptions &Options,
64 Reloc::Model RM, CodeModel::Model CM,
66 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
70 //===----------------------------------------------------------------------===//
71 // Pass Pipeline Configuration
72 //===----------------------------------------------------------------------===//
75 /// PPC Code Generator Pass Configuration Options.
76 class PPCPassConfig : public TargetPassConfig {
78 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
79 : TargetPassConfig(TM, PM) {}
81 PPCTargetMachine &getPPCTargetMachine() const {
82 return getTM<PPCTargetMachine>();
85 const PPCSubtarget &getPPCSubtarget() const {
86 return *getPPCTargetMachine().getSubtargetImpl();
89 bool addPreISel() override;
90 bool addILPOpts() override;
91 bool addInstSelector() override;
92 bool addPreRegAlloc() override;
93 bool addPreSched2() override;
94 bool addPreEmitPass() override;
98 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
99 return new PPCPassConfig(this, PM);
102 bool PPCPassConfig::addPreISel() {
103 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
104 addPass(createPPCCTRLoops(getPPCTargetMachine()));
109 bool PPCPassConfig::addILPOpts() {
110 addPass(&EarlyIfConverterID);
114 bool PPCPassConfig::addInstSelector() {
115 // Install an instruction selector.
116 addPass(createPPCISelDag(getPPCTargetMachine()));
119 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
120 addPass(createPPCCTRLoopsVerify());
123 addPass(createPPCVSXCopyPass());
127 bool PPCPassConfig::addPreRegAlloc() {
128 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
129 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
134 bool PPCPassConfig::addPreSched2() {
135 addPass(createPPCVSXCopyCleanupPass());
137 if (getOptLevel() != CodeGenOpt::None)
138 addPass(&IfConverterID);
143 bool PPCPassConfig::addPreEmitPass() {
144 if (getOptLevel() != CodeGenOpt::None)
145 addPass(createPPCEarlyReturnPass());
146 // Must run branch selection immediately preceding the asm printer.
147 addPass(createPPCBranchSelectionPass());
151 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
152 JITCodeEmitter &JCE) {
153 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
155 Subtarget.SetJITMode();
157 // Machine code emitter pass for PowerPC.
158 PM.add(createPPCJITCodeEmitterPass(*this, JCE));
163 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
164 // Add first the target-independent BasicTTI pass, then our PPC pass. This
165 // allows the PPC pass to delegate to the target independent layer when
167 PM.add(createBasicTargetTransformInfoPass(this));
168 PM.add(createPPCTargetTransformInfoPass(this));