1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
24 extern "C" void LLVMInitializePowerPCTarget() {
25 // Register the targets
26 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
27 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
30 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
31 StringRef CPU, StringRef FS,
32 const TargetOptions &Options,
33 Reloc::Model RM, CodeModel::Model CM,
36 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
37 Subtarget(TT, CPU, FS, is64Bit),
38 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
39 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
40 TLInfo(*this), TSInfo(*this),
41 InstrItins(Subtarget.getInstrItineraryData()) {
44 void PPC32TargetMachine::anchor() { }
46 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
47 StringRef CPU, StringRef FS,
48 const TargetOptions &Options,
49 Reloc::Model RM, CodeModel::Model CM,
51 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
54 void PPC64TargetMachine::anchor() { }
56 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
57 StringRef CPU, StringRef FS,
58 const TargetOptions &Options,
59 Reloc::Model RM, CodeModel::Model CM,
61 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
65 //===----------------------------------------------------------------------===//
66 // Pass Pipeline Configuration
67 //===----------------------------------------------------------------------===//
70 /// PPC Code Generator Pass Configuration Options.
71 class PPCPassConfig : public TargetPassConfig {
73 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
74 : TargetPassConfig(TM, PM) {}
76 PPCTargetMachine &getPPCTargetMachine() const {
77 return getTM<PPCTargetMachine>();
80 virtual bool addInstSelector();
81 virtual bool addPreEmitPass();
85 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
86 TargetPassConfig *PassConfig = new PPCPassConfig(this, PM);
88 // Override this for PowerPC. Tail merging happily breaks up instruction issue
89 // groups, which typically degrades performance.
90 PassConfig->setEnableTailMerge(false);
95 bool PPCPassConfig::addInstSelector() {
96 // Install an instruction selector.
97 PM.add(createPPCISelDag(getPPCTargetMachine()));
101 bool PPCPassConfig::addPreEmitPass() {
102 // Must run branch selection immediately preceding the asm printer.
103 PM.add(createPPCBranchSelectionPass());
107 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
108 JITCodeEmitter &JCE) {
109 // FIXME: This should be moved to TargetJITInfo!!
110 if (Subtarget.isPPC64())
111 // Temporary workaround for the inability of PPC64 JIT to handle jump
113 Options.DisableJumpTables = true;
115 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
117 Subtarget.SetJITMode();
119 // Machine code emitter pass for PowerPC.
120 PM.add(createPPCJITCodeEmitterPass(*this, JCE));