1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
29 extern "C" void LLVMInitializePowerPCTarget() {
30 // Register the targets
31 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
36 /// Return the datalayout string of a subtarget.
37 static std::string getDataLayoutString(const PPCSubtarget &ST) {
38 const Triple &T = ST.getTargetTriple();
42 // Most PPC* platforms are big endian, PPC64LE is little endian.
43 if (ST.isLittleEndian())
48 Ret += DataLayout::getManglingComponent(T);
50 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
52 if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
55 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
56 // documentation are wrong; these are correct (i.e. "what gcc does").
57 if (ST.isPPC64() || ST.isSVR4ABI())
62 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
71 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
72 StringRef CPU, StringRef FS,
73 const TargetOptions &Options,
74 Reloc::Model RM, CodeModel::Model CM,
77 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
78 Subtarget(TT, CPU, FS, is64Bit, OL),
79 DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
80 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
81 TLInfo(*this), TSInfo(*this),
82 InstrItins(Subtarget.getInstrItineraryData()) {
86 void PPC32TargetMachine::anchor() { }
88 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
89 StringRef CPU, StringRef FS,
90 const TargetOptions &Options,
91 Reloc::Model RM, CodeModel::Model CM,
93 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
96 void PPC64TargetMachine::anchor() { }
98 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
99 StringRef CPU, StringRef FS,
100 const TargetOptions &Options,
101 Reloc::Model RM, CodeModel::Model CM,
102 CodeGenOpt::Level OL)
103 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
107 //===----------------------------------------------------------------------===//
108 // Pass Pipeline Configuration
109 //===----------------------------------------------------------------------===//
112 /// PPC Code Generator Pass Configuration Options.
113 class PPCPassConfig : public TargetPassConfig {
115 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
116 : TargetPassConfig(TM, PM) {}
118 PPCTargetMachine &getPPCTargetMachine() const {
119 return getTM<PPCTargetMachine>();
122 const PPCSubtarget &getPPCSubtarget() const {
123 return *getPPCTargetMachine().getSubtargetImpl();
126 virtual bool addPreISel();
127 virtual bool addILPOpts();
128 virtual bool addInstSelector();
129 virtual bool addPreSched2();
130 virtual bool addPreEmitPass();
134 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
135 return new PPCPassConfig(this, PM);
138 bool PPCPassConfig::addPreISel() {
139 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
140 addPass(createPPCCTRLoops(getPPCTargetMachine()));
145 bool PPCPassConfig::addILPOpts() {
146 if (getPPCSubtarget().hasISEL()) {
147 addPass(&EarlyIfConverterID);
154 bool PPCPassConfig::addInstSelector() {
155 // Install an instruction selector.
156 addPass(createPPCISelDag(getPPCTargetMachine()));
159 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
160 addPass(createPPCCTRLoopsVerify());
163 if (getPPCSubtarget().hasVSX())
164 addPass(createPPCVSXCopyPass());
169 bool PPCPassConfig::addPreSched2() {
170 if (getOptLevel() != CodeGenOpt::None)
171 addPass(&IfConverterID);
176 bool PPCPassConfig::addPreEmitPass() {
177 if (getOptLevel() != CodeGenOpt::None)
178 addPass(createPPCEarlyReturnPass());
179 // Must run branch selection immediately preceding the asm printer.
180 addPass(createPPCBranchSelectionPass());
184 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
185 JITCodeEmitter &JCE) {
186 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
188 Subtarget.SetJITMode();
190 // Machine code emitter pass for PowerPC.
191 PM.add(createPPCJITCodeEmitterPass(*this, JCE));
196 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
197 // Add first the target-independent BasicTTI pass, then our PPC pass. This
198 // allows the PPC pass to delegate to the target independent layer when
200 PM.add(createBasicTargetTransformInfoPass(this));
201 PM.add(createPPCTargetTransformInfoPass(this));