1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "PPCTargetObjectFile.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/PassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Transforms/Scalar.h"
29 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
30 cl::desc("Disable CTR loops for PPC"));
33 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
34 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
37 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
38 cl::desc("Enable optimizations on complex GEPs"),
41 extern "C" void LLVMInitializePowerPCTarget() {
42 // Register the targets
43 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
44 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
45 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
48 /// Return the datalayout string of a subtarget.
49 static std::string getDataLayoutString(const Triple &T) {
50 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
53 // Most PPC* platforms are big endian, PPC64LE is little endian.
54 if (T.getArch() == Triple::ppc64le)
59 Ret += DataLayout::getManglingComponent(T);
61 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
63 if (!is64Bit || T.getOS() == Triple::Lv2)
66 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
67 // documentation are wrong; these are correct (i.e. "what gcc does").
68 if (is64Bit || !T.isOSDarwin())
73 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
82 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
83 std::string FullFS = FS;
84 Triple TargetTriple(TT);
86 // Make sure 64-bit features are available when CPUname is generic
87 if (TargetTriple.getArch() == Triple::ppc64 ||
88 TargetTriple.getArch() == Triple::ppc64le) {
90 FullFS = "+64bit," + FullFS;
95 if (OL >= CodeGenOpt::Default) {
97 FullFS = "+crbits," + FullFS;
102 if (OL != CodeGenOpt::None) {
104 FullFS = "+invariant-function-descriptors," + FullFS;
106 FullFS = "+invariant-function-descriptors";
112 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
113 // If it isn't a Mach-O file then it's going to be a linux ELF
116 return make_unique<TargetLoweringObjectFileMachO>();
118 return make_unique<PPC64LinuxTargetObjectFile>();
121 // The FeatureString here is a little subtle. We are modifying the feature string
122 // with what are (currently) non-function specific overrides as it goes into the
123 // LLVMTargetMachine constructor and then using the stored value in the
124 // Subtarget constructor below it.
125 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
126 StringRef FS, const TargetOptions &Options,
127 Reloc::Model RM, CodeModel::Model CM,
128 CodeGenOpt::Level OL)
129 : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
131 TLOF(createTLOF(Triple(getTargetTriple()))),
132 DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) {
136 PPCTargetMachine::~PPCTargetMachine() {}
138 void PPC32TargetMachine::anchor() { }
140 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
141 StringRef CPU, StringRef FS,
142 const TargetOptions &Options,
143 Reloc::Model RM, CodeModel::Model CM,
144 CodeGenOpt::Level OL)
145 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
148 void PPC64TargetMachine::anchor() { }
150 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
151 StringRef CPU, StringRef FS,
152 const TargetOptions &Options,
153 Reloc::Model RM, CodeModel::Model CM,
154 CodeGenOpt::Level OL)
155 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
159 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
160 AttributeSet FnAttrs = F.getAttributes();
162 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
164 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
166 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
167 ? CPUAttr.getValueAsString().str()
169 std::string FS = !FSAttr.hasAttribute(Attribute::None)
170 ? FSAttr.getValueAsString().str()
173 auto &I = SubtargetMap[CPU + FS];
175 // This needs to be done before we create a new subtarget since any
176 // creation will depend on the TM and the code generation flags on the
177 // function that reside in TargetOptions.
178 resetTargetOptions(F);
179 I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
184 //===----------------------------------------------------------------------===//
185 // Pass Pipeline Configuration
186 //===----------------------------------------------------------------------===//
189 /// PPC Code Generator Pass Configuration Options.
190 class PPCPassConfig : public TargetPassConfig {
192 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
193 : TargetPassConfig(TM, PM) {}
195 PPCTargetMachine &getPPCTargetMachine() const {
196 return getTM<PPCTargetMachine>();
199 const PPCSubtarget &getPPCSubtarget() const {
200 return *getPPCTargetMachine().getSubtargetImpl();
203 void addIRPasses() override;
204 bool addPreISel() override;
205 bool addILPOpts() override;
206 bool addInstSelector() override;
207 void addPreRegAlloc() override;
208 void addPreSched2() override;
209 void addPreEmitPass() override;
213 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
214 return new PPCPassConfig(this, PM);
217 void PPCPassConfig::addIRPasses() {
218 addPass(createAtomicExpandPass(&getPPCTargetMachine()));
220 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
221 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
222 // and lower a GEP with multiple indices to either arithmetic operations or
223 // multiple GEPs with single index.
224 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
225 // Call EarlyCSE pass to find and remove subexpressions in the lowered
227 addPass(createEarlyCSEPass());
228 // Do loop invariant code motion in case part of the lowered result is
230 addPass(createLICMPass());
233 TargetPassConfig::addIRPasses();
236 bool PPCPassConfig::addPreISel() {
237 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
238 addPass(createPPCCTRLoops(getPPCTargetMachine()));
243 bool PPCPassConfig::addILPOpts() {
244 addPass(&EarlyIfConverterID);
248 bool PPCPassConfig::addInstSelector() {
249 // Install an instruction selector.
250 addPass(createPPCISelDag(getPPCTargetMachine()));
253 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
254 addPass(createPPCCTRLoopsVerify());
257 addPass(createPPCVSXCopyPass());
261 void PPCPassConfig::addPreRegAlloc() {
262 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
263 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
267 void PPCPassConfig::addPreSched2() {
268 addPass(createPPCVSXCopyCleanupPass(), false);
270 if (getOptLevel() != CodeGenOpt::None)
271 addPass(&IfConverterID);
274 void PPCPassConfig::addPreEmitPass() {
275 if (getOptLevel() != CodeGenOpt::None)
276 addPass(createPPCEarlyReturnPass(), false);
277 // Must run branch selection immediately preceding the asm printer.
278 addPass(createPPCBranchSelectionPass(), false);
281 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
282 // Add first the target-independent BasicTTI pass, then our PPC pass. This
283 // allows the PPC pass to delegate to the target independent layer when
285 PM.add(createBasicTargetTransformInfoPass(this));
286 PM.add(createPPCTargetTransformInfoPass(this));