1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
30 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
31 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
33 extern "C" void LLVMInitializePowerPCTarget() {
34 // Register the targets
35 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
36 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
37 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
40 /// Return the datalayout string of a subtarget.
41 static std::string getDataLayoutString(const PPCSubtarget &ST) {
42 const Triple &T = ST.getTargetTriple();
46 // Most PPC* platforms are big endian, PPC64LE is little endian.
47 if (ST.isLittleEndian())
52 Ret += DataLayout::getManglingComponent(T);
54 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
56 if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
59 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
60 // documentation are wrong; these are correct (i.e. "what gcc does").
61 if (ST.isPPC64() || ST.isSVR4ABI())
66 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
75 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
76 StringRef FS, const TargetOptions &Options,
77 Reloc::Model RM, CodeModel::Model CM,
78 CodeGenOpt::Level OL, bool is64Bit)
79 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
80 Subtarget(TT, CPU, FS, is64Bit, OL), DL(getDataLayoutString(Subtarget)),
81 InstrInfo(*this), JITInfo(*this, is64Bit), TLInfo(*this), TSInfo(*this) {
85 void PPC32TargetMachine::anchor() { }
87 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
88 StringRef CPU, StringRef FS,
89 const TargetOptions &Options,
90 Reloc::Model RM, CodeModel::Model CM,
92 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
95 void PPC64TargetMachine::anchor() { }
97 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
98 StringRef CPU, StringRef FS,
99 const TargetOptions &Options,
100 Reloc::Model RM, CodeModel::Model CM,
101 CodeGenOpt::Level OL)
102 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
106 //===----------------------------------------------------------------------===//
107 // Pass Pipeline Configuration
108 //===----------------------------------------------------------------------===//
111 /// PPC Code Generator Pass Configuration Options.
112 class PPCPassConfig : public TargetPassConfig {
114 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
115 : TargetPassConfig(TM, PM) {}
117 PPCTargetMachine &getPPCTargetMachine() const {
118 return getTM<PPCTargetMachine>();
121 const PPCSubtarget &getPPCSubtarget() const {
122 return *getPPCTargetMachine().getSubtargetImpl();
125 bool addPreISel() override;
126 bool addILPOpts() override;
127 bool addInstSelector() override;
128 bool addPreRegAlloc() override;
129 bool addPreSched2() override;
130 bool addPreEmitPass() override;
134 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
135 return new PPCPassConfig(this, PM);
138 bool PPCPassConfig::addPreISel() {
139 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
140 addPass(createPPCCTRLoops(getPPCTargetMachine()));
145 bool PPCPassConfig::addILPOpts() {
146 addPass(&EarlyIfConverterID);
150 bool PPCPassConfig::addInstSelector() {
151 // Install an instruction selector.
152 addPass(createPPCISelDag(getPPCTargetMachine()));
155 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
156 addPass(createPPCCTRLoopsVerify());
159 addPass(createPPCVSXCopyPass());
163 bool PPCPassConfig::addPreRegAlloc() {
164 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
165 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
170 bool PPCPassConfig::addPreSched2() {
171 addPass(createPPCVSXCopyCleanupPass());
173 if (getOptLevel() != CodeGenOpt::None)
174 addPass(&IfConverterID);
179 bool PPCPassConfig::addPreEmitPass() {
180 if (getOptLevel() != CodeGenOpt::None)
181 addPass(createPPCEarlyReturnPass());
182 // Must run branch selection immediately preceding the asm printer.
183 addPass(createPPCBranchSelectionPass());
187 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
188 JITCodeEmitter &JCE) {
189 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
191 Subtarget.SetJITMode();
193 // Machine code emitter pass for PowerPC.
194 PM.add(createPPCJITCodeEmitterPass(*this, JCE));
199 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
200 // Add first the target-independent BasicTTI pass, then our PPC pass. This
201 // allows the PPC pass to delegate to the target independent layer when
203 PM.add(createBasicTargetTransformInfoPass(this));
204 PM.add(createPPCTargetTransformInfoPass(this));