1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
15 #include "PPCTargetAsmInfo.h"
16 #include "PPCTargetMachine.h"
17 #include "llvm/Module.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Target/TargetMachineRegistry.h"
20 #include "llvm/Target/TargetOptions.h"
23 // Register the targets
24 static RegisterTarget<PPC32TargetMachine>
25 X("ppc32", " PowerPC 32");
26 static RegisterTarget<PPC64TargetMachine>
27 Y("ppc64", " PowerPC 64");
29 // No assembler printer by default
30 PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0;
32 const TargetAsmInfo *PPCTargetMachine::createTargetAsmInfo() const {
33 if (Subtarget.isDarwin())
34 return new PPCDarwinTargetAsmInfo(*this);
36 return new PPCLinuxTargetAsmInfo(*this);
39 unsigned PPC32TargetMachine::getJITMatchQuality() {
40 #if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) || defined(__PPC__)
41 if (sizeof(void*) == 4)
46 unsigned PPC64TargetMachine::getJITMatchQuality() {
47 #if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) || defined(__PPC__)
48 if (sizeof(void*) == 8)
54 unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
55 // We strongly match "powerpc-*".
56 std::string TT = M.getTargetTriple();
57 if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
60 // If the target triple is something non-powerpc, we don't match.
61 if (!TT.empty()) return 0;
63 if (M.getEndianness() == Module::BigEndian &&
64 M.getPointerSize() == Module::Pointer32)
65 return 10; // Weak match
66 else if (M.getEndianness() != Module::AnyEndianness ||
67 M.getPointerSize() != Module::AnyPointerSize)
68 return 0; // Match for some other target
70 return getJITMatchQuality()/2;
73 unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
74 // We strongly match "powerpc64-*".
75 std::string TT = M.getTargetTriple();
76 if (TT.size() >= 10 && std::string(TT.begin(), TT.begin()+10) == "powerpc64-")
79 if (M.getEndianness() == Module::BigEndian &&
80 M.getPointerSize() == Module::Pointer64)
81 return 10; // Weak match
82 else if (M.getEndianness() != Module::AnyEndianness ||
83 M.getPointerSize() != Module::AnyPointerSize)
84 return 0; // Match for some other target
86 return getJITMatchQuality()/2;
90 PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS,
92 : Subtarget(*this, M, FS, is64Bit),
93 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
94 FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
95 InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
97 if (getRelocationModel() == Reloc::Default) {
98 if (Subtarget.isDarwin())
99 setRelocationModel(Reloc::DynamicNoPIC);
101 setRelocationModel(Reloc::Static);
105 /// Override this for PowerPC. Tail merging happily breaks up instruction issue
106 /// groups, which typically degrades performance.
107 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
109 PPC32TargetMachine::PPC32TargetMachine(const Module &M, const std::string &FS)
110 : PPCTargetMachine(M, FS, false) {
114 PPC64TargetMachine::PPC64TargetMachine(const Module &M, const std::string &FS)
115 : PPCTargetMachine(M, FS, true) {
119 //===----------------------------------------------------------------------===//
120 // Pass Pipeline Configuration
121 //===----------------------------------------------------------------------===//
123 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
124 // Install an instruction selector.
125 PM.add(createPPCISelDag(*this));
129 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
131 // Must run branch selection immediately preceding the asm printer.
132 PM.add(createPPCBranchSelectionPass());
136 bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
138 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
140 PM.add(AsmPrinterCtor(Out, *this));
145 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
146 bool DumpAsm, MachineCodeEmitter &MCE) {
147 // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
148 // FIXME: This should be moved to TargetJITInfo!!
149 if (Subtarget.isPPC64()) {
150 // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
151 // instructions to materialize arbitrary global variable + function +
152 // constant pool addresses.
153 setRelocationModel(Reloc::PIC_);
154 // Temporary workaround for the inability of PPC64 JIT to handle jump
156 DisableJumpTables = true;
158 setRelocationModel(Reloc::Static);
161 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
163 Subtarget.SetJITMode();
165 // Machine code emitter pass for PowerPC.
166 PM.add(createPPCCodeEmitterPass(*this, MCE));
168 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
170 PM.add(AsmPrinterCtor(*cerr.stream(), *this));
176 bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
177 bool DumpAsm, MachineCodeEmitter &MCE) {
178 // Machine code emitter pass for PowerPC.
179 PM.add(createPPCCodeEmitterPass(*this, MCE));
181 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
183 PM.add(AsmPrinterCtor(*cerr.stream(), *this));