1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/FormattedStream.h"
22 #include "llvm/Support/TargetRegistry.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
29 extern "C" void LLVMInitializePowerPCTarget() {
30 // Register the targets
31 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
35 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
36 StringRef CPU, StringRef FS,
37 const TargetOptions &Options,
38 Reloc::Model RM, CodeModel::Model CM,
41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42 Subtarget(TT, CPU, FS, is64Bit),
43 DL(Subtarget.getDataLayoutString()), InstrInfo(*this),
44 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
45 TLInfo(*this), TSInfo(*this),
46 InstrItins(Subtarget.getInstrItineraryData()),
47 STTI(&TLInfo), VTTI(&TLInfo) {
49 // The binutils for the BG/P are too old for CFI.
50 if (Subtarget.isBGP())
54 void PPC32TargetMachine::anchor() { }
56 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
57 StringRef CPU, StringRef FS,
58 const TargetOptions &Options,
59 Reloc::Model RM, CodeModel::Model CM,
61 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
64 void PPC64TargetMachine::anchor() { }
66 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
67 StringRef CPU, StringRef FS,
68 const TargetOptions &Options,
69 Reloc::Model RM, CodeModel::Model CM,
71 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
75 //===----------------------------------------------------------------------===//
76 // Pass Pipeline Configuration
77 //===----------------------------------------------------------------------===//
80 /// PPC Code Generator Pass Configuration Options.
81 class PPCPassConfig : public TargetPassConfig {
83 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
84 : TargetPassConfig(TM, PM) {}
86 PPCTargetMachine &getPPCTargetMachine() const {
87 return getTM<PPCTargetMachine>();
90 virtual bool addPreRegAlloc();
91 virtual bool addInstSelector();
92 virtual bool addPreEmitPass();
96 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
97 return new PPCPassConfig(this, PM);
100 bool PPCPassConfig::addPreRegAlloc() {
101 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
102 addPass(createPPCCTRLoops());
107 bool PPCPassConfig::addInstSelector() {
108 // Install an instruction selector.
109 addPass(createPPCISelDag(getPPCTargetMachine()));
113 bool PPCPassConfig::addPreEmitPass() {
114 // Must run branch selection immediately preceding the asm printer.
115 addPass(createPPCBranchSelectionPass());
119 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
120 JITCodeEmitter &JCE) {
121 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
123 Subtarget.SetJITMode();
125 // Machine code emitter pass for PowerPC.
126 PM.add(createPPCJITCodeEmitterPass(*this, JCE));