1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
15 #include "PPCTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/Target/TargetOptions.h"
19 #include "llvm/Target/TargetRegistry.h"
20 #include "llvm/Support/FormattedStream.h"
23 // This is duplicated code. Refactor this.
24 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
25 MCContext &Ctx, TargetAsmBackend &TAB,
27 MCCodeEmitter *Emitter,
30 if (Triple(TT).isOSDarwin())
31 return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
36 extern "C" void LLVMInitializePowerPCTarget() {
37 // Register the targets
38 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
39 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
41 // Register the MC Code Emitter
42 TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
43 TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
46 // Register the asm backend.
47 TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend);
48 TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend);
50 // Register the object streamer.
51 TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer);
52 TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
55 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
56 StringRef CPU, StringRef FS,
57 Reloc::Model RM, CodeModel::Model CM,
59 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
60 Subtarget(TT, CPU, FS, is64Bit),
61 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
62 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
63 TLInfo(*this), TSInfo(*this),
64 InstrItins(Subtarget.getInstrItineraryData()) {
67 /// Override this for PowerPC. Tail merging happily breaks up instruction issue
68 /// groups, which typically degrades performance.
69 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
71 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
72 StringRef CPU, StringRef FS,
73 Reloc::Model RM, CodeModel::Model CM)
74 : PPCTargetMachine(T, TT, CPU, FS, RM, CM, false) {
78 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
79 StringRef CPU, StringRef FS,
80 Reloc::Model RM, CodeModel::Model CM)
81 : PPCTargetMachine(T, TT, CPU, FS, RM, CM, true) {
85 //===----------------------------------------------------------------------===//
86 // Pass Pipeline Configuration
87 //===----------------------------------------------------------------------===//
89 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
90 CodeGenOpt::Level OptLevel) {
91 // Install an instruction selector.
92 PM.add(createPPCISelDag(*this));
96 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
97 CodeGenOpt::Level OptLevel) {
98 // Must run branch selection immediately preceding the asm printer.
99 PM.add(createPPCBranchSelectionPass());
103 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
104 CodeGenOpt::Level OptLevel,
105 JITCodeEmitter &JCE) {
106 // FIXME: This should be moved to TargetJITInfo!!
107 if (Subtarget.isPPC64())
108 // Temporary workaround for the inability of PPC64 JIT to handle jump
110 DisableJumpTables = true;
112 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
114 Subtarget.SetJITMode();
116 // Machine code emitter pass for PowerPC.
117 PM.add(createPPCJITCodeEmitterPass(*this, JCE));