1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
30 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31 cl::desc("Disable CTR loops for PPC"));
34 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35 cl::desc("Disable PPC loop preinc prep"));
38 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
42 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
43 cl::desc("Disable VSX Swap Removal for PPC"));
46 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
47 cl::desc("Enable optimizations on complex GEPs"),
51 EnablePrefetch("enable-ppc-prefetching",
52 cl::desc("disable software prefetching on PPC"),
53 cl::init(false), cl::Hidden);
56 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
57 cl::desc("Add extra TOC register dependencies"),
58 cl::init(true), cl::Hidden);
60 extern "C" void LLVMInitializePowerPCTarget() {
61 // Register the targets
62 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
63 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
64 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
67 /// Return the datalayout string of a subtarget.
68 static std::string getDataLayoutString(const Triple &T) {
69 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
72 // Most PPC* platforms are big endian, PPC64LE is little endian.
73 if (T.getArch() == Triple::ppc64le)
78 Ret += DataLayout::getManglingComponent(T);
80 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
82 if (!is64Bit || T.getOS() == Triple::Lv2)
85 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
86 // documentation are wrong; these are correct (i.e. "what gcc does").
87 if (is64Bit || !T.isOSDarwin())
92 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
101 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
102 std::string FullFS = FS;
103 Triple TargetTriple(TT);
105 // Make sure 64-bit features are available when CPUname is generic
106 if (TargetTriple.getArch() == Triple::ppc64 ||
107 TargetTriple.getArch() == Triple::ppc64le) {
109 FullFS = "+64bit," + FullFS;
114 if (OL >= CodeGenOpt::Default) {
116 FullFS = "+crbits," + FullFS;
121 if (OL != CodeGenOpt::None) {
123 FullFS = "+invariant-function-descriptors," + FullFS;
125 FullFS = "+invariant-function-descriptors";
131 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
132 // If it isn't a Mach-O file then it's going to be a linux ELF
135 return make_unique<TargetLoweringObjectFileMachO>();
137 return make_unique<PPC64LinuxTargetObjectFile>();
140 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
141 const TargetOptions &Options) {
142 if (Options.MCOptions.getABIName().startswith("elfv1"))
143 return PPCTargetMachine::PPC_ABI_ELFv1;
144 else if (Options.MCOptions.getABIName().startswith("elfv2"))
145 return PPCTargetMachine::PPC_ABI_ELFv2;
147 assert(Options.MCOptions.getABIName().empty() &&
148 "Unknown target-abi option!");
150 if (!TT.isMacOSX()) {
151 switch (TT.getArch()) {
152 case Triple::ppc64le:
153 return PPCTargetMachine::PPC_ABI_ELFv2;
155 return PPCTargetMachine::PPC_ABI_ELFv1;
161 return PPCTargetMachine::PPC_ABI_UNKNOWN;
164 // The FeatureString here is a little subtle. We are modifying the feature string
165 // with what are (currently) non-function specific overrides as it goes into the
166 // LLVMTargetMachine constructor and then using the stored value in the
167 // Subtarget constructor below it.
168 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
169 StringRef FS, const TargetOptions &Options,
170 Reloc::Model RM, CodeModel::Model CM,
171 CodeGenOpt::Level OL)
172 : LLVMTargetMachine(T, getDataLayoutString(Triple(TT)), TT, CPU,
173 computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
174 TLOF(createTLOF(Triple(getTargetTriple()))),
175 TargetABI(computeTargetABI(Triple(TT), Options)) {
179 PPCTargetMachine::~PPCTargetMachine() {}
181 void PPC32TargetMachine::anchor() { }
183 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
184 StringRef CPU, StringRef FS,
185 const TargetOptions &Options,
186 Reloc::Model RM, CodeModel::Model CM,
187 CodeGenOpt::Level OL)
188 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
191 void PPC64TargetMachine::anchor() { }
193 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
194 StringRef CPU, StringRef FS,
195 const TargetOptions &Options,
196 Reloc::Model RM, CodeModel::Model CM,
197 CodeGenOpt::Level OL)
198 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
202 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
203 Attribute CPUAttr = F.getFnAttribute("target-cpu");
204 Attribute FSAttr = F.getFnAttribute("target-features");
206 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
207 ? CPUAttr.getValueAsString().str()
209 std::string FS = !FSAttr.hasAttribute(Attribute::None)
210 ? FSAttr.getValueAsString().str()
213 auto &I = SubtargetMap[CPU + FS];
215 // This needs to be done before we create a new subtarget since any
216 // creation will depend on the TM and the code generation flags on the
217 // function that reside in TargetOptions.
218 resetTargetOptions(F);
219 I = llvm::make_unique<PPCSubtarget>(
221 // FIXME: It would be good to have the subtarget additions here
222 // not necessary. Anything that turns them on/off (overrides) ends
223 // up being put at the end of the feature string, but the defaults
224 // shouldn't require adding them. Fixing this means pulling Feature64Bit
225 // out of most of the target cpus in the .td file and making it set only
226 // as part of initialization via the TargetTriple.
227 computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
232 //===----------------------------------------------------------------------===//
233 // Pass Pipeline Configuration
234 //===----------------------------------------------------------------------===//
237 /// PPC Code Generator Pass Configuration Options.
238 class PPCPassConfig : public TargetPassConfig {
240 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
241 : TargetPassConfig(TM, PM) {}
243 PPCTargetMachine &getPPCTargetMachine() const {
244 return getTM<PPCTargetMachine>();
247 void addIRPasses() override;
248 bool addPreISel() override;
249 bool addILPOpts() override;
250 bool addInstSelector() override;
251 void addMachineSSAOptimization() override;
252 void addPreRegAlloc() override;
253 void addPreSched2() override;
254 void addPreEmitPass() override;
258 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
259 return new PPCPassConfig(this, PM);
262 void PPCPassConfig::addIRPasses() {
263 addPass(createAtomicExpandPass(&getPPCTargetMachine()));
265 // For the BG/Q (or if explicitly requested), add explicit data prefetch
267 bool UsePrefetching =
268 Triple(TM->getTargetTriple()).getVendor() == Triple::BGQ &&
269 getOptLevel() != CodeGenOpt::None;
270 if (EnablePrefetch.getNumOccurrences() > 0)
271 UsePrefetching = EnablePrefetch;
273 addPass(createPPCLoopDataPrefetchPass());
275 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
276 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
277 // and lower a GEP with multiple indices to either arithmetic operations or
278 // multiple GEPs with single index.
279 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
280 // Call EarlyCSE pass to find and remove subexpressions in the lowered
282 addPass(createEarlyCSEPass());
283 // Do loop invariant code motion in case part of the lowered result is
285 addPass(createLICMPass());
288 TargetPassConfig::addIRPasses();
291 bool PPCPassConfig::addPreISel() {
292 if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
293 addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
295 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
296 addPass(createPPCCTRLoops(getPPCTargetMachine()));
301 bool PPCPassConfig::addILPOpts() {
302 addPass(&EarlyIfConverterID);
306 bool PPCPassConfig::addInstSelector() {
307 // Install an instruction selector.
308 addPass(createPPCISelDag(getPPCTargetMachine()));
311 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
312 addPass(createPPCCTRLoopsVerify());
315 addPass(createPPCVSXCopyPass());
319 void PPCPassConfig::addMachineSSAOptimization() {
320 TargetPassConfig::addMachineSSAOptimization();
321 // For little endian, remove where possible the vector swap instructions
322 // introduced at code generation to normalize vector element order.
323 if (Triple(TM->getTargetTriple()).getArch() == Triple::ppc64le &&
324 !DisableVSXSwapRemoval)
325 addPass(createPPCVSXSwapRemovalPass());
328 void PPCPassConfig::addPreRegAlloc() {
329 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
330 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
332 if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
333 addPass(createPPCTLSDynamicCallPass());
334 if (EnableExtraTOCRegDeps)
335 addPass(createPPCTOCRegDepsPass());
338 void PPCPassConfig::addPreSched2() {
339 if (getOptLevel() != CodeGenOpt::None)
340 addPass(&IfConverterID);
343 void PPCPassConfig::addPreEmitPass() {
344 if (getOptLevel() != CodeGenOpt::None)
345 addPass(createPPCEarlyReturnPass(), false);
346 // Must run branch selection immediately preceding the asm printer.
347 addPass(createPPCBranchSelectionPass(), false);
350 TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
351 return TargetIRAnalysis(
352 [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });