1 //===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "PowerPCTargetMachine.h"
15 #include "PowerPCFrameInfo.h"
16 #include "PPC32TargetMachine.h"
17 #include "PPC64TargetMachine.h"
18 #include "PPC32JITInfo.h"
19 #include "PPC64JITInfo.h"
20 #include "llvm/Module.h"
21 #include "llvm/PassManager.h"
22 #include "llvm/CodeGen/IntrinsicLowering.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Target/TargetMachineRegistry.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include "llvm/Support/CommandLine.h"
34 cl::opt<bool> AIX("aix",
35 cl::desc("Generate AIX/xcoff instead of Darwin/MachO"),
37 cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc",
38 cl::desc("Enable LSR for PPC (beta)"),
40 cl::opt<bool, true> EnablePPCCRopts("enable-cc-opts",
41 cl::desc("Enable opts using condition regs (beta)"),
42 cl::location(PPCCRopts),
48 const std::string PPC32ID = "PowerPC/32bit";
49 const std::string PPC64ID = "PowerPC/64bit";
51 // Register the targets
52 RegisterTarget<PPC32TargetMachine>
53 X("ppc32", " PowerPC 32-bit");
56 RegisterTarget<PPC64TargetMachine>
57 Y("ppc64", " PowerPC 64-bit (unimplemented)");
61 PowerPCTargetMachine::PowerPCTargetMachine(const std::string &name,
62 IntrinsicLowering *IL,
64 const PowerPCFrameInfo &TFI)
65 : TargetMachine(name, IL, TD), FrameInfo(TFI)
68 unsigned PPC32TargetMachine::getJITMatchQuality() {
69 #if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
76 /// addPassesToEmitAssembly - Add passes to the specified pass manager
77 /// to implement a static compiler for this target.
79 bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
81 bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(this));
84 PM.add(createLoopStrengthReducePass());
85 PM.add(createCFGSimplificationPass());
88 // FIXME: Implement efficient support for garbage collection intrinsics.
89 PM.add(createLowerGCPass());
91 // FIXME: Implement the invoke/unwind instructions!
92 PM.add(createLowerInvokePass());
94 // FIXME: Implement the switch instruction in the instruction selector!
95 PM.add(createLowerSwitchPass());
97 PM.add(createLowerConstantExpressionsPass());
99 // Make sure that no unreachable blocks are instruction selected.
100 PM.add(createUnreachableBlockEliminationPass());
102 // Default to pattern ISel
104 PM.add(createPPC64ISelPattern(*this));
105 else if (PatternISelTriState == 0)
106 PM.add(createPPC32ISelSimple(*this));
108 PM.add(createPPC32ISelPattern(*this));
110 if (PrintMachineCode)
111 PM.add(createMachineFunctionPrinterPass(&std::cerr));
113 PM.add(createRegisterAllocator());
115 if (PrintMachineCode)
116 PM.add(createMachineFunctionPrinterPass(&std::cerr));
118 PM.add(createPrologEpilogCodeInserter());
120 // Must run branch selection immediately preceding the asm printer
121 PM.add(createPPCBranchSelectionPass());
124 PM.add(createAIXAsmPrinter(Out, *this));
126 PM.add(createDarwinAsmPrinter(Out, *this));
128 PM.add(createMachineCodeDeleter());
132 void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
133 bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(&TM));
136 PM.add(createLoopStrengthReducePass());
137 PM.add(createCFGSimplificationPass());
140 // FIXME: Implement efficient support for garbage collection intrinsics.
141 PM.add(createLowerGCPass());
143 // FIXME: Implement the invoke/unwind instructions!
144 PM.add(createLowerInvokePass());
146 // FIXME: Implement the switch instruction in the instruction selector!
147 PM.add(createLowerSwitchPass());
149 PM.add(createLowerConstantExpressionsPass());
151 // Make sure that no unreachable blocks are instruction selected.
152 PM.add(createUnreachableBlockEliminationPass());
154 // Default to pattern ISel
156 PM.add(createPPC64ISelPattern(TM));
157 else if (PatternISelTriState == 0)
158 PM.add(createPPC32ISelSimple(TM));
160 PM.add(createPPC32ISelPattern(TM));
162 PM.add(createRegisterAllocator());
163 PM.add(createPrologEpilogCodeInserter());
165 // Must run branch selection immediately preceding the asm printer
166 PM.add(createPPCBranchSelectionPass());
168 if (PrintMachineCode)
169 PM.add(createMachineFunctionPrinterPass(&std::cerr));
172 /// PowerPCTargetMachine ctor - Create an ILP32 architecture model
174 PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL)
175 : PowerPCTargetMachine(PPC32ID, IL,
176 TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
177 PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
179 /// PPC64TargetMachine ctor - Create a LP64 architecture model
181 PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL)
182 : PowerPCTargetMachine(PPC64ID, IL,
183 TargetData(PPC64ID,false,8,4,4,4,4,4,2,1,1),
184 PowerPCFrameInfo(*this, true)) {}
186 unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
187 // We strongly match "powerpc-*".
188 std::string TT = M.getTargetTriple();
189 if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
192 if (M.getEndianness() == Module::BigEndian &&
193 M.getPointerSize() == Module::Pointer32)
194 return 10; // Weak match
195 else if (M.getEndianness() != Module::AnyEndianness ||
196 M.getPointerSize() != Module::AnyPointerSize)
197 return 0; // Match for some other target
199 return getJITMatchQuality()/2;
202 unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
203 if (M.getEndianness() == Module::BigEndian &&
204 M.getPointerSize() == Module::Pointer64)
205 return 10; // Direct match
206 else if (M.getEndianness() != Module::AnyEndianness ||
207 M.getPointerSize() != Module::AnyPointerSize)
208 return 0; // Match for some other target
210 return getJITMatchQuality()/2;