1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
15 #include "PPCTargetObjectFile.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/PassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
28 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
29 cl::desc("Disable CTR loops for PPC"));
32 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
33 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
35 extern "C" void LLVMInitializePowerPCTarget() {
36 // Register the targets
37 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
38 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
39 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
42 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
43 std::string FullFS = FS;
44 Triple TargetTriple(TT);
46 // Make sure 64-bit features are available when CPUname is generic
47 if (TargetTriple.getArch() == Triple::ppc64 ||
48 TargetTriple.getArch() == Triple::ppc64le) {
50 FullFS = "+64bit," + FullFS;
55 if (OL >= CodeGenOpt::Default) {
57 FullFS = "+crbits," + FullFS;
64 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
65 // If it isn't a Mach-O file then it's going to be a linux ELF
68 return make_unique<TargetLoweringObjectFileMachO>();
70 return make_unique<PPC64LinuxTargetObjectFile>();
73 // The FeatureString here is a little subtle. We are modifying the feature string
74 // with what are (currently) non-function specific overrides as it goes into the
75 // LLVMTargetMachine constructor and then using the stored value in the
76 // Subtarget constructor below it.
77 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
78 StringRef FS, const TargetOptions &Options,
79 Reloc::Model RM, CodeModel::Model CM,
81 : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
83 TLOF(createTLOF(Triple(getTargetTriple()))),
84 Subtarget(TT, CPU, TargetFS, *this) {
88 PPCTargetMachine::~PPCTargetMachine() {}
90 void PPC32TargetMachine::anchor() { }
92 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
93 StringRef CPU, StringRef FS,
94 const TargetOptions &Options,
95 Reloc::Model RM, CodeModel::Model CM,
97 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
100 void PPC64TargetMachine::anchor() { }
102 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
103 StringRef CPU, StringRef FS,
104 const TargetOptions &Options,
105 Reloc::Model RM, CodeModel::Model CM,
106 CodeGenOpt::Level OL)
107 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
111 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
112 AttributeSet FnAttrs = F.getAttributes();
114 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
116 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
118 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
119 ? CPUAttr.getValueAsString().str()
121 std::string FS = !FSAttr.hasAttribute(Attribute::None)
122 ? FSAttr.getValueAsString().str()
125 auto &I = SubtargetMap[CPU + FS];
127 // This needs to be done before we create a new subtarget since any
128 // creation will depend on the TM and the code generation flags on the
129 // function that reside in TargetOptions.
130 resetTargetOptions(F);
131 I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
136 //===----------------------------------------------------------------------===//
137 // Pass Pipeline Configuration
138 //===----------------------------------------------------------------------===//
141 /// PPC Code Generator Pass Configuration Options.
142 class PPCPassConfig : public TargetPassConfig {
144 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
145 : TargetPassConfig(TM, PM) {}
147 PPCTargetMachine &getPPCTargetMachine() const {
148 return getTM<PPCTargetMachine>();
151 const PPCSubtarget &getPPCSubtarget() const {
152 return *getPPCTargetMachine().getSubtargetImpl();
155 void addIRPasses() override;
156 bool addPreISel() override;
157 bool addILPOpts() override;
158 bool addInstSelector() override;
159 bool addPreRegAlloc() override;
160 bool addPreSched2() override;
161 bool addPreEmitPass() override;
165 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
166 return new PPCPassConfig(this, PM);
169 void PPCPassConfig::addIRPasses() {
170 addPass(createAtomicExpandPass(&getPPCTargetMachine()));
171 TargetPassConfig::addIRPasses();
174 bool PPCPassConfig::addPreISel() {
175 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
176 addPass(createPPCCTRLoops(getPPCTargetMachine()));
181 bool PPCPassConfig::addILPOpts() {
182 addPass(&EarlyIfConverterID);
186 bool PPCPassConfig::addInstSelector() {
187 // Install an instruction selector.
188 addPass(createPPCISelDag(getPPCTargetMachine()));
191 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
192 addPass(createPPCCTRLoopsVerify());
195 addPass(createPPCVSXCopyPass());
199 bool PPCPassConfig::addPreRegAlloc() {
200 initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
201 insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
206 bool PPCPassConfig::addPreSched2() {
207 addPass(createPPCVSXCopyCleanupPass());
209 if (getOptLevel() != CodeGenOpt::None)
210 addPass(&IfConverterID);
215 bool PPCPassConfig::addPreEmitPass() {
216 if (getOptLevel() != CodeGenOpt::None)
217 addPass(createPPCEarlyReturnPass());
218 // Must run branch selection immediately preceding the asm printer.
219 addPass(createPPCBranchSelectionPass());
223 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
224 // Add first the target-independent BasicTTI pass, then our PPC pass. This
225 // allows the PPC pass to delegate to the target independent layer when
227 PM.add(createBasicTargetTransformInfoPass(this));
228 PM.add(createPPCTargetTransformInfoPass(this));