1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
29 extern "C" void LLVMInitializePowerPCTarget() {
30 // Register the targets
31 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
36 /// Return the datalayout string of a subtarget.
37 static std::string getDataLayoutString(const PPCSubtarget &ST) {
39 std::string Ret = "E";
41 // PPC32 has 32 bit pointers.
45 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
46 // documentation are wrong; these are correct (i.e. "what gcc does").
49 // Set support for 128 floats depending on the ABI.
50 if (!ST.isPPC64() || !ST.isSVR4ABI())
51 Ret += "-f128:64:128";
53 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
62 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
63 StringRef CPU, StringRef FS,
64 const TargetOptions &Options,
65 Reloc::Model RM, CodeModel::Model CM,
68 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
69 Subtarget(TT, CPU, FS, is64Bit),
70 DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
71 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
72 TLInfo(*this), TSInfo(*this),
73 InstrItins(Subtarget.getInstrItineraryData()) {
75 // The binutils for the BG/P are too old for CFI.
76 if (Subtarget.isBGP())
81 void PPC32TargetMachine::anchor() { }
83 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
84 StringRef CPU, StringRef FS,
85 const TargetOptions &Options,
86 Reloc::Model RM, CodeModel::Model CM,
88 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
91 void PPC64TargetMachine::anchor() { }
93 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
94 StringRef CPU, StringRef FS,
95 const TargetOptions &Options,
96 Reloc::Model RM, CodeModel::Model CM,
98 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
102 //===----------------------------------------------------------------------===//
103 // Pass Pipeline Configuration
104 //===----------------------------------------------------------------------===//
107 /// PPC Code Generator Pass Configuration Options.
108 class PPCPassConfig : public TargetPassConfig {
110 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
111 : TargetPassConfig(TM, PM) {}
113 PPCTargetMachine &getPPCTargetMachine() const {
114 return getTM<PPCTargetMachine>();
117 const PPCSubtarget &getPPCSubtarget() const {
118 return *getPPCTargetMachine().getSubtargetImpl();
121 virtual bool addPreISel();
122 virtual bool addILPOpts();
123 virtual bool addInstSelector();
124 virtual bool addPreSched2();
125 virtual bool addPreEmitPass();
129 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
130 return new PPCPassConfig(this, PM);
133 bool PPCPassConfig::addPreISel() {
134 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
135 addPass(createPPCCTRLoops(getPPCTargetMachine()));
140 bool PPCPassConfig::addILPOpts() {
141 if (getPPCSubtarget().hasISEL()) {
142 addPass(&EarlyIfConverterID);
149 bool PPCPassConfig::addInstSelector() {
150 // Install an instruction selector.
151 addPass(createPPCISelDag(getPPCTargetMachine()));
154 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
155 addPass(createPPCCTRLoopsVerify());
161 bool PPCPassConfig::addPreSched2() {
162 if (getOptLevel() != CodeGenOpt::None)
163 addPass(&IfConverterID);
168 bool PPCPassConfig::addPreEmitPass() {
169 if (getOptLevel() != CodeGenOpt::None)
170 addPass(createPPCEarlyReturnPass());
171 // Must run branch selection immediately preceding the asm printer.
172 addPass(createPPCBranchSelectionPass());
176 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
177 JITCodeEmitter &JCE) {
178 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
180 Subtarget.SetJITMode();
182 // Machine code emitter pass for PowerPC.
183 PM.add(createPPCJITCodeEmitterPass(*this, JCE));
188 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
189 // Add first the target-independent BasicTTI pass, then our PPC pass. This
190 // allows the PPC pass to delegate to the target independent layer when
192 PM.add(createBasicTargetTransformInfoPass(this));
193 PM.add(createPPCTargetTransformInfoPass(this));