1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// PPC target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
18 #include "PPCTargetMachine.h"
19 #include "llvm/Analysis/TargetTransformInfo.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/CostTable.h"
23 #include "llvm/Target/TargetLowering.h"
26 #define DEBUG_TYPE "ppctti"
28 static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
29 cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
31 // Declare the pass initialization routine locally as target-specific passes
32 // don't have a target-wide initialization entry point, and so we rely on the
33 // pass constructor initialization.
35 void initializePPCTTIPass(PassRegistry &);
40 class PPCTTI final : public ImmutablePass, public TargetTransformInfo {
41 const PPCSubtarget *ST;
42 const PPCTargetLowering *TLI;
45 PPCTTI() : ImmutablePass(ID), ST(nullptr), TLI(nullptr) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 PPCTTI(const PPCTargetMachine *TM)
50 : ImmutablePass(ID), ST(TM->getSubtargetImpl()),
51 TLI(TM->getSubtargetImpl()->getTargetLowering()) {
52 initializePPCTTIPass(*PassRegistry::getPassRegistry());
55 void initializePass() override {
59 void getAnalysisUsage(AnalysisUsage &AU) const override {
60 TargetTransformInfo::getAnalysisUsage(AU);
63 /// Pass identification.
66 /// Provide necessary pointer adjustments for the two base classes.
67 void *getAdjustedAnalysisPointer(const void *ID) override {
68 if (ID == &TargetTransformInfo::ID)
69 return (TargetTransformInfo*)this;
73 /// \name Scalar TTI Implementations
75 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
77 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
78 Type *Ty) const override;
79 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
80 Type *Ty) const override;
82 PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override;
83 void getUnrollingPreferences(
84 Loop *L, UnrollingPreferences &UP) const override;
88 /// \name Vector TTI Implementations
91 unsigned getNumberOfRegisters(bool Vector) const override;
92 unsigned getRegisterBitWidth(bool Vector) const override;
93 unsigned getMaximumUnrollFactor() const override;
94 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind,
95 OperandValueKind, OperandValueProperties,
96 OperandValueProperties) const override;
97 unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
98 int Index, Type *SubTp) const override;
99 unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
100 Type *Src) const override;
101 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
102 Type *CondTy) const override;
103 unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
104 unsigned Index) const override;
105 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
106 unsigned AddressSpace) const override;
111 } // end anonymous namespace
113 INITIALIZE_AG_PASS(PPCTTI, TargetTransformInfo, "ppctti",
114 "PPC Target Transform Info", true, true, false)
118 llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) {
119 return new PPCTTI(TM);
123 //===----------------------------------------------------------------------===//
127 //===----------------------------------------------------------------------===//
129 PPCTTI::PopcntSupportKind PPCTTI::getPopcntSupport(unsigned TyWidth) const {
130 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
131 if (ST->hasPOPCNTD() && TyWidth <= 64)
132 return PSK_FastHardware;
136 unsigned PPCTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
137 if (DisablePPCConstHoist)
138 return TargetTransformInfo::getIntImmCost(Imm, Ty);
140 assert(Ty->isIntegerTy());
142 unsigned BitSize = Ty->getPrimitiveSizeInBits();
149 if (Imm.getBitWidth() <= 64) {
150 if (isInt<16>(Imm.getSExtValue()))
153 if (isInt<32>(Imm.getSExtValue())) {
154 // A constant that can be materialized using lis.
155 if ((Imm.getZExtValue() & 0xFFFF) == 0)
158 return 2 * TCC_Basic;
162 return 4 * TCC_Basic;
165 unsigned PPCTTI::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
166 const APInt &Imm, Type *Ty) const {
167 if (DisablePPCConstHoist)
168 return TargetTransformInfo::getIntImmCost(IID, Idx, Imm, Ty);
170 assert(Ty->isIntegerTy());
172 unsigned BitSize = Ty->getPrimitiveSizeInBits();
177 default: return TCC_Free;
178 case Intrinsic::sadd_with_overflow:
179 case Intrinsic::uadd_with_overflow:
180 case Intrinsic::ssub_with_overflow:
181 case Intrinsic::usub_with_overflow:
182 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue()))
186 return PPCTTI::getIntImmCost(Imm, Ty);
189 unsigned PPCTTI::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
191 if (DisablePPCConstHoist)
192 return TargetTransformInfo::getIntImmCost(Opcode, Idx, Imm, Ty);
194 assert(Ty->isIntegerTy());
196 unsigned BitSize = Ty->getPrimitiveSizeInBits();
200 unsigned ImmIdx = ~0U;
201 bool ShiftedFree = false, RunFree = false, UnsignedFree = false,
204 default: return TCC_Free;
205 case Instruction::GetElementPtr:
206 // Always hoist the base address of a GetElementPtr. This prevents the
207 // creation of new constants for every base constant that gets constant
208 // folded with the offset.
210 return 2 * TCC_Basic;
212 case Instruction::And:
213 RunFree = true; // (for the rotate-and-mask instructions)
215 case Instruction::Add:
216 case Instruction::Or:
217 case Instruction::Xor:
220 case Instruction::Sub:
221 case Instruction::Mul:
222 case Instruction::Shl:
223 case Instruction::LShr:
224 case Instruction::AShr:
227 case Instruction::ICmp:
230 // Fallthrough... (zero comparisons can use record-form instructions)
231 case Instruction::Select:
234 case Instruction::PHI:
235 case Instruction::Call:
236 case Instruction::Ret:
237 case Instruction::Load:
238 case Instruction::Store:
242 if (ZeroFree && Imm == 0)
245 if (Idx == ImmIdx && Imm.getBitWidth() <= 64) {
246 if (isInt<16>(Imm.getSExtValue()))
250 if (Imm.getBitWidth() <= 32 &&
251 (isShiftedMask_32(Imm.getZExtValue()) ||
252 isShiftedMask_32(~Imm.getZExtValue())))
257 (isShiftedMask_64(Imm.getZExtValue()) ||
258 isShiftedMask_64(~Imm.getZExtValue())))
262 if (UnsignedFree && isUInt<16>(Imm.getZExtValue()))
265 if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0)
269 return PPCTTI::getIntImmCost(Imm, Ty);
272 void PPCTTI::getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const {
273 if (ST->getDarwinDirective() == PPC::DIR_A2) {
274 // The A2 is in-order with a deep pipeline, and concatenation unrolling
275 // helps expose latency-hiding opportunities to the instruction scheduler.
276 UP.Partial = UP.Runtime = true;
280 unsigned PPCTTI::getNumberOfRegisters(bool Vector) const {
281 if (Vector && !ST->hasAltivec())
283 return ST->hasVSX() ? 64 : 32;
286 unsigned PPCTTI::getRegisterBitWidth(bool Vector) const {
288 if (ST->hasAltivec()) return 128;
298 unsigned PPCTTI::getMaximumUnrollFactor() const {
299 unsigned Directive = ST->getDarwinDirective();
300 // The 440 has no SIMD support, but floating-point instructions
301 // have a 5-cycle latency, so unroll by 5x for latency hiding.
302 if (Directive == PPC::DIR_440)
305 // The A2 has no SIMD support, but floating-point instructions
306 // have a 6-cycle latency, so unroll by 6x for latency hiding.
307 if (Directive == PPC::DIR_A2)
310 // FIXME: For lack of any better information, do no harm...
311 if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
314 // For most things, modern systems have two execution units (and
315 // out-of-order execution).
319 unsigned PPCTTI::getArithmeticInstrCost(
320 unsigned Opcode, Type *Ty, OperandValueKind Op1Info,
321 OperandValueKind Op2Info, OperandValueProperties Opd1PropInfo,
322 OperandValueProperties Opd2PropInfo) const {
323 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
325 // Fallback to the default implementation.
326 return TargetTransformInfo::getArithmeticInstrCost(
327 Opcode, Ty, Op1Info, Op2Info, Opd1PropInfo, Opd2PropInfo);
330 unsigned PPCTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
332 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
335 unsigned PPCTTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
336 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
338 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
341 unsigned PPCTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
342 Type *CondTy) const {
343 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
346 unsigned PPCTTI::getVectorInstrCost(unsigned Opcode, Type *Val,
347 unsigned Index) const {
348 assert(Val->isVectorTy() && "This must be a vector type");
350 int ISD = TLI->InstructionOpcodeToISD(Opcode);
351 assert(ISD && "Invalid opcode");
353 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
354 // Double-precision scalars are already located in index #0.
358 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
361 // Estimated cost of a load-hit-store delay. This was obtained
362 // experimentally as a minimum needed to prevent unprofitable
363 // vectorization for the paq8p benchmark. It may need to be
364 // raised further if other unprofitable cases remain.
365 unsigned LHSPenalty = 2;
366 if (ISD == ISD::INSERT_VECTOR_ELT)
369 // Vector element insert/extract with Altivec is very expensive,
370 // because they require store and reload with the attendant
371 // processor stall for load-hit-store. Until VSX is available,
372 // these need to be estimated as very costly.
373 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
374 ISD == ISD::INSERT_VECTOR_ELT)
376 TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
378 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
381 unsigned PPCTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
382 unsigned AddressSpace) const {
383 // Legalize the type.
384 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
385 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
389 TargetTransformInfo::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
391 // VSX loads/stores support unaligned access.
393 if (LT.second == MVT::v2f64 || LT.second == MVT::v2i64)
397 bool UnalignedAltivec =
399 Src->getPrimitiveSizeInBits() >= LT.second.getSizeInBits() &&
400 LT.second.getSizeInBits() == 128 &&
401 Opcode == Instruction::Load;
403 // PPC in general does not support unaligned loads and stores. They'll need
404 // to be decomposed based on the alignment factor.
405 unsigned SrcBytes = LT.second.getStoreSize();
406 if (SrcBytes && Alignment && Alignment < SrcBytes && !UnalignedAltivec) {
407 Cost += LT.first*(SrcBytes/Alignment-1);
409 // For a vector type, there is also scalarization overhead (only for
410 // stores, loads are expanded using the vector-load + permutation sequence,
411 // which is much less expensive).
412 if (Src->isVectorTy() && Opcode == Instruction::Store)
413 for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
414 Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);