1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// PPC target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "ppctti"
19 #include "PPCTargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/CostTable.h"
23 #include "llvm/Target/TargetLowering.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializePPCTTIPass(PassRegistry &);
35 class PPCTTI : public ImmutablePass, public TargetTransformInfo {
36 const PPCTargetMachine *TM;
37 const PPCSubtarget *ST;
38 const PPCTargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 PPCTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 PPCTTI(const PPCTargetMachine *TM)
50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializePPCTTIPass(*PassRegistry::getPassRegistry());
55 virtual void initializePass() {
59 virtual void finalizePass() {
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 TargetTransformInfo::getAnalysisUsage(AU);
67 /// Pass identification.
70 /// Provide necessary pointer adjustments for the two base classes.
71 virtual void *getAdjustedAnalysisPointer(const void *ID) {
72 if (ID == &TargetTransformInfo::ID)
73 return (TargetTransformInfo*)this;
77 /// \name Scalar TTI Implementations
79 virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const;
80 virtual void getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const;
84 /// \name Vector TTI Implementations
87 virtual unsigned getNumberOfRegisters(bool Vector) const;
88 virtual unsigned getRegisterBitWidth(bool Vector) const;
89 virtual unsigned getMaximumUnrollFactor() const;
90 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
92 OperandValueKind) const;
93 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
94 int Index, Type *SubTp) const;
95 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
97 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
99 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
100 unsigned Index) const;
101 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
103 unsigned AddressSpace) const;
108 } // end anonymous namespace
110 INITIALIZE_AG_PASS(PPCTTI, TargetTransformInfo, "ppctti",
111 "PPC Target Transform Info", true, true, false)
115 llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) {
116 return new PPCTTI(TM);
120 //===----------------------------------------------------------------------===//
124 //===----------------------------------------------------------------------===//
126 PPCTTI::PopcntSupportKind PPCTTI::getPopcntSupport(unsigned TyWidth) const {
127 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
128 if (ST->hasPOPCNTD() && TyWidth <= 64)
129 return PSK_FastHardware;
133 void PPCTTI::getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const {
134 if (ST->getDarwinDirective() == PPC::DIR_A2) {
135 // The A2 is in-order with a deep pipeline, and concatenation unrolling
136 // helps expose latency-hiding opportunities to the instruction scheduler.
137 UP.Partial = UP.Runtime = true;
141 unsigned PPCTTI::getNumberOfRegisters(bool Vector) const {
142 if (Vector && !ST->hasAltivec())
147 unsigned PPCTTI::getRegisterBitWidth(bool Vector) const {
149 if (ST->hasAltivec()) return 128;
159 unsigned PPCTTI::getMaximumUnrollFactor() const {
160 unsigned Directive = ST->getDarwinDirective();
161 // The 440 has no SIMD support, but floating-point instructions
162 // have a 5-cycle latency, so unroll by 5x for latency hiding.
163 if (Directive == PPC::DIR_440)
166 // The A2 has no SIMD support, but floating-point instructions
167 // have a 6-cycle latency, so unroll by 6x for latency hiding.
168 if (Directive == PPC::DIR_A2)
171 // FIXME: For lack of any better information, do no harm...
172 if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
175 // For most things, modern systems have two execution units (and
176 // out-of-order execution).
180 unsigned PPCTTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
181 OperandValueKind Op1Info,
182 OperandValueKind Op2Info) const {
183 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
185 // Fallback to the default implementation.
186 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
190 unsigned PPCTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
192 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
195 unsigned PPCTTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
196 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
198 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
201 unsigned PPCTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
202 Type *CondTy) const {
203 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
206 unsigned PPCTTI::getVectorInstrCost(unsigned Opcode, Type *Val,
207 unsigned Index) const {
208 assert(Val->isVectorTy() && "This must be a vector type");
210 int ISD = TLI->InstructionOpcodeToISD(Opcode);
211 assert(ISD && "Invalid opcode");
213 // Estimated cost of a load-hit-store delay. This was obtained
214 // experimentally as a minimum needed to prevent unprofitable
215 // vectorization for the paq8p benchmark. It may need to be
216 // raised further if other unprofitable cases remain.
217 unsigned LHSPenalty = 12;
219 // Vector element insert/extract with Altivec is very expensive,
220 // because they require store and reload with the attendant
221 // processor stall for load-hit-store. Until VSX is available,
222 // these need to be estimated as very costly.
223 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
224 ISD == ISD::INSERT_VECTOR_ELT)
226 TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
228 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
231 unsigned PPCTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
232 unsigned AddressSpace) const {
233 // Legalize the type.
234 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
235 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
238 // Each load/store unit costs 1.
239 unsigned Cost = LT.first * 1;
241 // PPC in general does not support unaligned loads and stores. They'll need
242 // to be decomposed based on the alignment factor.
243 unsigned SrcBytes = LT.second.getStoreSize();
244 if (SrcBytes && Alignment && Alignment < SrcBytes)
245 Cost *= (SrcBytes/Alignment);