1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// PPC target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "ppctti"
19 #include "PPCTargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/CostTable.h"
23 #include "llvm/Target/TargetLowering.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializePPCTTIPass(PassRegistry &);
35 class PPCTTI final : public ImmutablePass, public TargetTransformInfo {
36 const PPCSubtarget *ST;
37 const PPCTargetLowering *TLI;
40 PPCTTI() : ImmutablePass(ID), ST(0), TLI(0) {
41 llvm_unreachable("This pass cannot be directly constructed");
44 PPCTTI(const PPCTargetMachine *TM)
45 : ImmutablePass(ID), ST(TM->getSubtargetImpl()),
46 TLI(TM->getTargetLowering()) {
47 initializePPCTTIPass(*PassRegistry::getPassRegistry());
50 virtual void initializePass() override {
54 virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
55 TargetTransformInfo::getAnalysisUsage(AU);
58 /// Pass identification.
61 /// Provide necessary pointer adjustments for the two base classes.
62 virtual void *getAdjustedAnalysisPointer(const void *ID) override {
63 if (ID == &TargetTransformInfo::ID)
64 return (TargetTransformInfo*)this;
68 /// \name Scalar TTI Implementations
70 virtual PopcntSupportKind
71 getPopcntSupport(unsigned TyWidth) const override;
72 virtual void getUnrollingPreferences(
73 Loop *L, UnrollingPreferences &UP) const override;
77 /// \name Vector TTI Implementations
80 virtual unsigned getNumberOfRegisters(bool Vector) const override;
81 virtual unsigned getRegisterBitWidth(bool Vector) const override;
82 virtual unsigned getMaximumUnrollFactor() const override;
83 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
85 OperandValueKind) const override;
86 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
87 int Index, Type *SubTp) const override;
88 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
89 Type *Src) const override;
90 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
91 Type *CondTy) const override;
92 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
93 unsigned Index) const override;
94 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
96 unsigned AddressSpace) const override;
101 } // end anonymous namespace
103 INITIALIZE_AG_PASS(PPCTTI, TargetTransformInfo, "ppctti",
104 "PPC Target Transform Info", true, true, false)
108 llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) {
109 return new PPCTTI(TM);
113 //===----------------------------------------------------------------------===//
117 //===----------------------------------------------------------------------===//
119 PPCTTI::PopcntSupportKind PPCTTI::getPopcntSupport(unsigned TyWidth) const {
120 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
121 if (ST->hasPOPCNTD() && TyWidth <= 64)
122 return PSK_FastHardware;
126 void PPCTTI::getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const {
127 if (ST->getDarwinDirective() == PPC::DIR_A2) {
128 // The A2 is in-order with a deep pipeline, and concatenation unrolling
129 // helps expose latency-hiding opportunities to the instruction scheduler.
130 UP.Partial = UP.Runtime = true;
134 unsigned PPCTTI::getNumberOfRegisters(bool Vector) const {
135 if (Vector && !ST->hasAltivec())
137 return ST->hasVSX() ? 64 : 32;
140 unsigned PPCTTI::getRegisterBitWidth(bool Vector) const {
142 if (ST->hasAltivec()) return 128;
152 unsigned PPCTTI::getMaximumUnrollFactor() const {
153 unsigned Directive = ST->getDarwinDirective();
154 // The 440 has no SIMD support, but floating-point instructions
155 // have a 5-cycle latency, so unroll by 5x for latency hiding.
156 if (Directive == PPC::DIR_440)
159 // The A2 has no SIMD support, but floating-point instructions
160 // have a 6-cycle latency, so unroll by 6x for latency hiding.
161 if (Directive == PPC::DIR_A2)
164 // FIXME: For lack of any better information, do no harm...
165 if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
168 // For most things, modern systems have two execution units (and
169 // out-of-order execution).
173 unsigned PPCTTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
174 OperandValueKind Op1Info,
175 OperandValueKind Op2Info) const {
176 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
178 // Fallback to the default implementation.
179 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
183 unsigned PPCTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
185 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
188 unsigned PPCTTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
189 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
191 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
194 unsigned PPCTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
195 Type *CondTy) const {
196 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
199 unsigned PPCTTI::getVectorInstrCost(unsigned Opcode, Type *Val,
200 unsigned Index) const {
201 assert(Val->isVectorTy() && "This must be a vector type");
203 int ISD = TLI->InstructionOpcodeToISD(Opcode);
204 assert(ISD && "Invalid opcode");
206 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
207 // Double-precision scalars are already located in index #0.
211 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
214 // Estimated cost of a load-hit-store delay. This was obtained
215 // experimentally as a minimum needed to prevent unprofitable
216 // vectorization for the paq8p benchmark. It may need to be
217 // raised further if other unprofitable cases remain.
218 unsigned LHSPenalty = 2;
219 if (ISD == ISD::INSERT_VECTOR_ELT)
222 // Vector element insert/extract with Altivec is very expensive,
223 // because they require store and reload with the attendant
224 // processor stall for load-hit-store. Until VSX is available,
225 // these need to be estimated as very costly.
226 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
227 ISD == ISD::INSERT_VECTOR_ELT)
229 TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
231 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
234 unsigned PPCTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
235 unsigned AddressSpace) const {
236 // Legalize the type.
237 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
238 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
242 TargetTransformInfo::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
244 // VSX loads/stores support unaligned access.
246 if (LT.second == MVT::v2f64 || LT.second == MVT::v2i64)
250 bool UnalignedAltivec =
252 Src->getPrimitiveSizeInBits() >= LT.second.getSizeInBits() &&
253 LT.second.getSizeInBits() == 128 &&
254 Opcode == Instruction::Load;
256 // PPC in general does not support unaligned loads and stores. They'll need
257 // to be decomposed based on the alignment factor.
258 unsigned SrcBytes = LT.second.getStoreSize();
259 if (SrcBytes && Alignment && Alignment < SrcBytes && !UnalignedAltivec) {
260 Cost += LT.first*(SrcBytes/Alignment-1);
262 // For a vector type, there is also scalarization overhead (only for
263 // stores, loads are expanded using the vector-load + permutation sequence,
264 // which is much less expensive).
265 if (Src->isVectorTy() && Opcode == Instruction::Store)
266 for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
267 Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);