1 //===----------- PPCVSXSwapRemoval.cpp - Remove VSX LE Swaps -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===---------------------------------------------------------------------===//
10 // This pass analyzes vector computations and removes unnecessary
11 // doubleword swaps (xxswapd instructions). This pass is performed
12 // only for little-endian VSX code generation.
14 // For this specific case, loads and stores of v4i32, v4f32, v2i64,
15 // and v2f64 vectors are inefficient. These are implemented using
16 // the lxvd2x and stxvd2x instructions, which invert the order of
17 // doublewords in a vector register. Thus code generation inserts
18 // an xxswapd after each such load, and prior to each such store.
20 // The extra xxswapd instructions reduce performance. The purpose
21 // of this pass is to reduce the number of xxswapd instructions
22 // required for correctness.
24 // The primary insight is that much code that operates on vectors
25 // does not care about the relative order of elements in a register,
26 // so long as the correct memory order is preserved. If we have a
27 // computation where all input values are provided by lxvd2x/xxswapd,
28 // all outputs are stored using xxswapd/lxvd2x, and all intermediate
29 // computations are lane-insensitive (independent of element order),
30 // then all the xxswapd instructions associated with the loads and
31 // stores may be removed without changing observable semantics.
33 // This pass uses standard equivalence class infrastructure to create
34 // maximal webs of computations fitting the above description. Each
35 // such web is then optimized by removing its unnecessary xxswapd
38 // There are some lane-sensitive operations for which we can still
39 // permit the optimization, provided we modify those operations
40 // accordingly. Such operations are identified as using "special
41 // handling" within this module.
43 //===---------------------------------------------------------------------===//
45 #include "PPCInstrInfo.h"
47 #include "PPCInstrBuilder.h"
48 #include "PPCTargetMachine.h"
49 #include "llvm/ADT/DenseMap.h"
50 #include "llvm/ADT/EquivalenceClasses.h"
51 #include "llvm/CodeGen/MachineFunctionPass.h"
52 #include "llvm/CodeGen/MachineInstrBuilder.h"
53 #include "llvm/CodeGen/MachineRegisterInfo.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/Format.h"
56 #include "llvm/Support/raw_ostream.h"
60 #define DEBUG_TYPE "ppc-vsx-swaps"
63 void initializePPCVSXSwapRemovalPass(PassRegistry&);
68 // A PPCVSXSwapEntry is created for each machine instruction that
69 // is relevant to a vector computation.
70 struct PPCVSXSwapEntry {
71 // Pointer to the instruction.
74 // Unique ID (position in the swap vector).
77 // Attributes of this node.
78 unsigned int IsLoad : 1;
79 unsigned int IsStore : 1;
80 unsigned int IsSwap : 1;
81 unsigned int MentionsPhysVR : 1;
82 unsigned int HasImplicitSubreg : 1;
83 unsigned int IsSwappable : 1;
84 unsigned int SpecialHandling : 3;
85 unsigned int WebRejected : 1;
86 unsigned int WillRemove : 1;
98 struct PPCVSXSwapRemoval : public MachineFunctionPass {
101 const PPCInstrInfo *TII;
103 MachineRegisterInfo *MRI;
105 // Swap entries are allocated in a vector for better performance.
106 std::vector<PPCVSXSwapEntry> SwapVector;
108 // A mapping is maintained between machine instructions and
109 // their swap entries. The key is the address of the MI.
110 DenseMap<MachineInstr*, int> SwapMap;
112 // Equivalence classes are used to gather webs of related computation.
113 // Swap entries are represented by their VSEId fields.
114 EquivalenceClasses<int> *EC;
116 PPCVSXSwapRemoval() : MachineFunctionPass(ID) {
117 initializePPCVSXSwapRemovalPass(*PassRegistry::getPassRegistry());
121 // Initialize data structures.
122 void initialize(MachineFunction &MFParm);
124 // Walk the machine instructions to gather vector usage information.
125 // Return true iff vector mentions are present.
126 bool gatherVectorInstructions();
128 // Add an entry to the swap vector and swap map.
129 int addSwapEntry(MachineInstr *MI, PPCVSXSwapEntry &SwapEntry);
131 // Hunt backwards through COPY and SUBREG_TO_REG chains for a
132 // source register. VecIdx indicates the swap vector entry to
133 // mark as mentioning a physical register if the search leads
135 unsigned lookThruCopyLike(unsigned SrcReg, unsigned VecIdx);
137 // Generate equivalence classes for related computations (webs).
140 // Analyze webs and determine those that cannot be optimized.
141 void recordUnoptimizableWebs();
143 // Record which swap instructions can be safely removed.
144 void markSwapsForRemoval();
146 // Remove swaps and update other instructions requiring special
147 // handling. Return true iff any changes are made.
150 // Update instructions requiring special handling.
151 void handleSpecialSwappables(int EntryIdx);
153 // Dump a description of the entries in the swap vector.
154 void dumpSwapVector();
156 // Return true iff the given register is in the given class.
157 bool isRegInClass(unsigned Reg, const TargetRegisterClass *RC) {
158 if (TargetRegisterInfo::isVirtualRegister(Reg))
159 return RC->hasSubClassEq(MRI->getRegClass(Reg));
160 if (RC->contains(Reg))
165 // Return true iff the given register is a full vector register.
166 bool isVecReg(unsigned Reg) {
167 return (isRegInClass(Reg, &PPC::VSRCRegClass) ||
168 isRegInClass(Reg, &PPC::VRRCRegClass));
172 // Main entry point for this pass.
173 bool runOnMachineFunction(MachineFunction &MF) override {
174 // If we don't have VSX on the subtarget, don't do anything.
175 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
179 bool Changed = false;
182 if (gatherVectorInstructions()) {
184 recordUnoptimizableWebs();
185 markSwapsForRemoval();
186 Changed = removeSwaps();
189 // FIXME: See the allocation of EC in initialize().
195 // Initialize data structures for this pass. In particular, clear the
196 // swap vector and allocate the equivalence class mapping before
197 // processing each function.
198 void PPCVSXSwapRemoval::initialize(MachineFunction &MFParm) {
200 MRI = &MF->getRegInfo();
201 TII = static_cast<const PPCInstrInfo*>(MF->getSubtarget().getInstrInfo());
203 // An initial vector size of 256 appears to work well in practice.
204 // Small/medium functions with vector content tend not to incur a
205 // reallocation at this size. Three of the vector tests in
206 // projects/test-suite reallocate, which seems like a reasonable rate.
207 const int InitialVectorSize(256);
209 SwapVector.reserve(InitialVectorSize);
211 // FIXME: Currently we allocate EC each time because we don't have
212 // access to the set representation on which to call clear(). Should
213 // consider adding a clear() method to the EquivalenceClasses class.
214 EC = new EquivalenceClasses<int>;
217 // Create an entry in the swap vector for each instruction that mentions
218 // a full vector register, recording various characteristics of the
219 // instructions there.
220 bool PPCVSXSwapRemoval::gatherVectorInstructions() {
221 bool RelevantFunction = false;
223 for (MachineBasicBlock &MBB : *MF) {
224 for (MachineInstr &MI : MBB) {
226 bool RelevantInstr = false;
227 bool ImplicitSubreg = false;
229 for (const MachineOperand &MO : MI.operands()) {
232 unsigned Reg = MO.getReg();
234 RelevantInstr = true;
235 if (MO.getSubReg() != 0)
236 ImplicitSubreg = true;
244 RelevantFunction = true;
246 // Create a SwapEntry initialized to zeros, then fill in the
247 // instruction and ID fields before pushing it to the back
248 // of the swap vector.
249 PPCVSXSwapEntry SwapEntry{};
250 int VecIdx = addSwapEntry(&MI, SwapEntry);
253 SwapVector[VecIdx].HasImplicitSubreg = 1;
255 switch(MI.getOpcode()) {
257 // Unless noted otherwise, an instruction is considered
258 // safe for the optimization. There are a large number of
259 // such true-SIMD instructions (all vector math, logical,
260 // select, compare, etc.).
261 SwapVector[VecIdx].IsSwappable = 1;
264 // This is a swap if it is of the form XXPERMDI t, s, s, 2.
265 // Unfortunately, MachineCSE ignores COPY and SUBREG_TO_REG, so we
266 // can also see XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), 2,
267 // for example. We have to look through chains of COPY and
268 // SUBREG_TO_REG to find the real source value for comparison.
269 // If the real source value is a physical register, then mark the
270 // XXPERMDI as mentioning a physical register.
271 // Any other form of XXPERMDI is lane-sensitive and unsafe
272 // for the optimization.
273 if (MI.getOperand(3).getImm() == 2) {
274 unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
276 unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
278 if (trueReg1 == trueReg2)
279 SwapVector[VecIdx].IsSwap = 1;
283 // Non-permuting loads are currently unsafe. We can use special
284 // handling for this in the future. By not marking these as
285 // IsSwap, we ensure computations containing them will be rejected
287 SwapVector[VecIdx].IsLoad = 1;
291 // Permuting loads are marked as both load and swap, and are
292 // safe for optimization.
293 SwapVector[VecIdx].IsLoad = 1;
294 SwapVector[VecIdx].IsSwap = 1;
297 // Non-permuting stores are currently unsafe. We can use special
298 // handling for this in the future. By not marking these as
299 // IsSwap, we ensure computations containing them will be rejected
301 SwapVector[VecIdx].IsStore = 1;
305 // Permuting stores are marked as both store and swap, and are
306 // safe for optimization.
307 SwapVector[VecIdx].IsStore = 1;
308 SwapVector[VecIdx].IsSwap = 1;
310 case PPC::SUBREG_TO_REG:
311 // These are fine provided they are moving between full vector
312 // register classes. For example, the VRs are a subset of the
313 // VSRs, but each VR and each VSR is a full 128-bit register.
314 if (isVecReg(MI.getOperand(0).getReg()) &&
315 isVecReg(MI.getOperand(2).getReg()))
316 SwapVector[VecIdx].IsSwappable = 1;
319 // These are fine provided they are moving between full vector
321 if (isVecReg(MI.getOperand(0).getReg()) &&
322 isVecReg(MI.getOperand(1).getReg()))
323 SwapVector[VecIdx].IsSwappable = 1;
328 // Splats are lane-sensitive, but we can use special handling
329 // to adjust the source lane for the splat. This is not yet
330 // implemented. When it is, we need to uncomment the following:
331 SwapVector[VecIdx].IsSwappable = 1;
332 SwapVector[VecIdx].SpecialHandling = SHValues::SH_SPLAT;
334 // The presence of the following lane-sensitive operations in a
335 // web will kill the optimization, at least for now. For these
336 // we do nothing, causing the optimization to fail.
337 // FIXME: Some of these could be permitted with special handling,
338 // and will be phased in as time permits.
339 // FIXME: There is no simple and maintainable way to express a set
340 // of opcodes having a common attribute in TableGen. Should this
341 // change, this is a prime candidate to use such a mechanism.
343 case PPC::EXTRACT_SUBREG:
344 case PPC::INSERT_SUBREG:
345 case PPC::COPY_TO_REGCLASS:
359 case PPC::VCIPHERLAST:
379 case PPC::VNCIPHERLAST:
404 case PPC::VSHASIGMAD:
405 case PPC::VSHASIGMAW:
432 if (RelevantFunction) {
433 DEBUG(dbgs() << "Swap vector when first built\n\n");
437 return RelevantFunction;
440 // Add an entry to the swap vector and swap map, and make a
441 // singleton equivalence class for the entry.
442 int PPCVSXSwapRemoval::addSwapEntry(MachineInstr *MI,
443 PPCVSXSwapEntry& SwapEntry) {
444 SwapEntry.VSEMI = MI;
445 SwapEntry.VSEId = SwapVector.size();
446 SwapVector.push_back(SwapEntry);
447 EC->insert(SwapEntry.VSEId);
448 SwapMap[MI] = SwapEntry.VSEId;
449 return SwapEntry.VSEId;
452 // This is used to find the "true" source register for an
453 // XXPERMDI instruction, since MachineCSE does not handle the
454 // "copy-like" operations (Copy and SubregToReg). Returns
455 // the original SrcReg unless it is the target of a copy-like
456 // operation, in which case we chain backwards through all
457 // such operations to the ultimate source register. If a
458 // physical register is encountered, we stop the search and
459 // flag the swap entry indicated by VecIdx (the original
460 // XXPERMDI) as mentioning a physical register. Similarly
461 // for implicit subregister mentions (which should never
463 unsigned PPCVSXSwapRemoval::lookThruCopyLike(unsigned SrcReg,
465 MachineInstr *MI = MRI->getVRegDef(SrcReg);
466 if (!MI->isCopyLike())
469 unsigned CopySrcReg, CopySrcSubreg;
471 CopySrcReg = MI->getOperand(1).getReg();
472 CopySrcSubreg = MI->getOperand(1).getSubReg();
474 assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike");
475 CopySrcReg = MI->getOperand(2).getReg();
476 CopySrcSubreg = MI->getOperand(2).getSubReg();
479 if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg)) {
480 SwapVector[VecIdx].MentionsPhysVR = 1;
484 if (CopySrcSubreg != 0) {
485 SwapVector[VecIdx].HasImplicitSubreg = 1;
489 return lookThruCopyLike(CopySrcReg, VecIdx);
492 // Generate equivalence classes for related computations (webs) by
493 // def-use relationships of virtual registers. Mention of a physical
494 // register terminates the generation of equivalence classes as this
495 // indicates a use of a parameter, definition of a return value, use
496 // of a value returned from a call, or definition of a parameter to a
497 // call. Computations with physical register mentions are flagged
498 // as such so their containing webs will not be optimized.
499 void PPCVSXSwapRemoval::formWebs() {
501 DEBUG(dbgs() << "\n*** Forming webs for swap removal ***\n\n");
503 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
505 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
507 DEBUG(dbgs() << "\n" << SwapVector[EntryIdx].VSEId << " ");
510 // It's sufficient to walk vector uses and join them to their unique
511 // definitions. In addition, check *all* vector register operands
512 // for physical regs.
513 for (const MachineOperand &MO : MI->operands()) {
517 unsigned Reg = MO.getReg();
521 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
522 SwapVector[EntryIdx].MentionsPhysVR = 1;
529 MachineInstr* DefMI = MRI->getVRegDef(Reg);
530 assert(SwapMap.find(DefMI) != SwapMap.end() &&
531 "Inconsistency: def of vector reg not found in swap map!");
532 int DefIdx = SwapMap[DefMI];
533 (void)EC->unionSets(SwapVector[DefIdx].VSEId,
534 SwapVector[EntryIdx].VSEId);
536 DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[DefIdx].VSEId,
537 SwapVector[EntryIdx].VSEId));
538 DEBUG(dbgs() << " Def: ");
539 DEBUG(DefMI->dump());
544 // Walk the swap vector entries looking for conditions that prevent their
545 // containing computations from being optimized. When such conditions are
546 // found, mark the representative of the computation's equivalence class
548 void PPCVSXSwapRemoval::recordUnoptimizableWebs() {
550 DEBUG(dbgs() << "\n*** Rejecting webs for swap removal ***\n\n");
552 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
553 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
555 // Reject webs containing mentions of physical registers or implicit
556 // subregs, or containing operations that we don't know how to handle
557 // in a lane-permuted region.
558 if (SwapVector[EntryIdx].MentionsPhysVR ||
559 SwapVector[EntryIdx].HasImplicitSubreg ||
560 !(SwapVector[EntryIdx].IsSwappable || SwapVector[EntryIdx].IsSwap)) {
562 SwapVector[Repr].WebRejected = 1;
565 format("Web %d rejected for physreg, subreg, or not swap[pable]\n",
567 DEBUG(dbgs() << " in " << EntryIdx << ": ");
568 DEBUG(SwapVector[EntryIdx].VSEMI->dump());
569 DEBUG(dbgs() << "\n");
572 // Reject webs than contain swapping loads that feed something other
573 // than a swap instruction.
574 else if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
575 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
576 unsigned DefReg = MI->getOperand(0).getReg();
578 // We skip debug instructions in the analysis. (Note that debug
579 // location information is still maintained by this optimization
580 // because it remains on the LXVD2X and STXVD2X instructions after
581 // the XXPERMDIs are removed.)
582 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
583 int UseIdx = SwapMap[&UseMI];
585 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad ||
586 SwapVector[UseIdx].IsStore) {
588 SwapVector[Repr].WebRejected = 1;
591 format("Web %d rejected for load not feeding swap\n", Repr));
592 DEBUG(dbgs() << " def " << EntryIdx << ": ");
594 DEBUG(dbgs() << " use " << UseIdx << ": ");
596 DEBUG(dbgs() << "\n");
600 // Reject webs than contain swapping stores that are fed by something
601 // other than a swap instruction.
602 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) {
603 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
604 unsigned UseReg = MI->getOperand(0).getReg();
605 MachineInstr *DefMI = MRI->getVRegDef(UseReg);
606 int DefIdx = SwapMap[DefMI];
608 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
609 SwapVector[DefIdx].IsStore) {
611 SwapVector[Repr].WebRejected = 1;
614 format("Web %d rejected for store not fed by swap\n", Repr));
615 DEBUG(dbgs() << " def " << DefIdx << ": ");
616 DEBUG(DefMI->dump());
617 DEBUG(dbgs() << " use " << EntryIdx << ": ");
619 DEBUG(dbgs() << "\n");
624 DEBUG(dbgs() << "Swap vector after web analysis:\n\n");
628 // Walk the swap vector entries looking for swaps fed by permuting loads
629 // and swaps that feed permuting stores. If the containing computation
630 // has not been marked rejected, mark each such swap for removal.
631 // (Removal is delayed in case optimization has disturbed the pattern,
632 // such that multiple loads feed the same swap, etc.)
633 void PPCVSXSwapRemoval::markSwapsForRemoval() {
635 DEBUG(dbgs() << "\n*** Marking swaps for removal ***\n\n");
637 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
639 if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
640 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
642 if (!SwapVector[Repr].WebRejected) {
643 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
644 unsigned DefReg = MI->getOperand(0).getReg();
646 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
647 int UseIdx = SwapMap[&UseMI];
648 SwapVector[UseIdx].WillRemove = 1;
650 DEBUG(dbgs() << "Marking swap fed by load for removal: ");
655 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) {
656 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
658 if (!SwapVector[Repr].WebRejected) {
659 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
660 unsigned UseReg = MI->getOperand(0).getReg();
661 MachineInstr *DefMI = MRI->getVRegDef(UseReg);
662 int DefIdx = SwapMap[DefMI];
663 SwapVector[DefIdx].WillRemove = 1;
665 DEBUG(dbgs() << "Marking swap feeding store for removal: ");
666 DEBUG(DefMI->dump());
669 } else if (SwapVector[EntryIdx].IsSwappable &&
670 SwapVector[EntryIdx].SpecialHandling != 0) {
671 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
673 if (!SwapVector[Repr].WebRejected)
674 handleSpecialSwappables(EntryIdx);
679 // The identified swap entry requires special handling to allow its
680 // containing computation to be optimized. Perform that handling
682 // FIXME: This code is to be phased in with subsequent patches.
683 void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
684 switch (SwapVector[EntryIdx].SpecialHandling) {
687 assert(false && "Unexpected special handling type");
690 // For splats based on an index into a vector, add N/2 modulo N
691 // to the index, where N is the number of vector elements.
692 case SHValues::SH_SPLAT: {
693 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
696 DEBUG(dbgs() << "Changing splat: ");
699 switch (MI->getOpcode()) {
701 assert(false && "Unexpected splat opcode");
702 case PPC::VSPLTB: NElts = 16; break;
703 case PPC::VSPLTH: NElts = 8; break;
704 case PPC::VSPLTW: NElts = 4; break;
707 unsigned EltNo = MI->getOperand(1).getImm();
708 EltNo = (EltNo + NElts / 2) % NElts;
709 MI->getOperand(1).setImm(EltNo);
711 DEBUG(dbgs() << " Into: ");
719 // Walk the swap vector and replace each entry marked for removal with
721 bool PPCVSXSwapRemoval::removeSwaps() {
723 DEBUG(dbgs() << "\n*** Removing swaps ***\n\n");
725 bool Changed = false;
727 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
728 if (SwapVector[EntryIdx].WillRemove) {
730 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
731 MachineBasicBlock *MBB = MI->getParent();
732 BuildMI(*MBB, MI, MI->getDebugLoc(),
733 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
734 .addOperand(MI->getOperand(1));
736 DEBUG(dbgs() << format("Replaced %d with copy: ",
737 SwapVector[EntryIdx].VSEId));
740 MI->eraseFromParent();
747 // For debug purposes, dump the contents of the swap vector.
748 void PPCVSXSwapRemoval::dumpSwapVector() {
750 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
752 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
753 int ID = SwapVector[EntryIdx].VSEId;
755 DEBUG(dbgs() << format("%6d", ID));
756 DEBUG(dbgs() << format("%6d", EC->getLeaderValue(ID)));
757 DEBUG(dbgs() << format(" BB#%3d", MI->getParent()->getNumber()));
758 DEBUG(dbgs() << format(" %14s ", TII->getName(MI->getOpcode())));
760 if (SwapVector[EntryIdx].IsLoad)
761 DEBUG(dbgs() << "load ");
762 if (SwapVector[EntryIdx].IsStore)
763 DEBUG(dbgs() << "store ");
764 if (SwapVector[EntryIdx].IsSwap)
765 DEBUG(dbgs() << "swap ");
766 if (SwapVector[EntryIdx].MentionsPhysVR)
767 DEBUG(dbgs() << "physreg ");
768 if (SwapVector[EntryIdx].HasImplicitSubreg)
769 DEBUG(dbgs() << "implsubreg ");
771 if (SwapVector[EntryIdx].IsSwappable) {
772 DEBUG(dbgs() << "swappable ");
773 switch(SwapVector[EntryIdx].SpecialHandling) {
775 DEBUG(dbgs() << "special:**unknown**");
780 DEBUG(dbgs() << "special:extract ");
783 DEBUG(dbgs() << "special:insert ");
786 DEBUG(dbgs() << "special:load ");
789 DEBUG(dbgs() << "special:store ");
792 DEBUG(dbgs() << "special:splat ");
797 if (SwapVector[EntryIdx].WebRejected)
798 DEBUG(dbgs() << "rejected ");
799 if (SwapVector[EntryIdx].WillRemove)
800 DEBUG(dbgs() << "remove ");
802 DEBUG(dbgs() << "\n");
804 // For no-asserts builds.
809 DEBUG(dbgs() << "\n");
814 INITIALIZE_PASS_BEGIN(PPCVSXSwapRemoval, DEBUG_TYPE,
815 "PowerPC VSX Swap Removal", false, false)
816 INITIALIZE_PASS_END(PPCVSXSwapRemoval, DEBUG_TYPE,
817 "PowerPC VSX Swap Removal", false, false)
819 char PPCVSXSwapRemoval::ID = 0;
821 llvm::createPPCVSXSwapRemovalPass() { return new PPCVSXSwapRemoval(); }