1 //===----------- PPCVSXSwapRemoval.cpp - Remove VSX LE Swaps -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===---------------------------------------------------------------------===//
10 // This pass analyzes vector computations and removes unnecessary
11 // doubleword swaps (xxswapd instructions). This pass is performed
12 // only for little-endian VSX code generation.
14 // For this specific case, loads and stores of v4i32, v4f32, v2i64,
15 // and v2f64 vectors are inefficient. These are implemented using
16 // the lxvd2x and stxvd2x instructions, which invert the order of
17 // doublewords in a vector register. Thus code generation inserts
18 // an xxswapd after each such load, and prior to each such store.
20 // The extra xxswapd instructions reduce performance. The purpose
21 // of this pass is to reduce the number of xxswapd instructions
22 // required for correctness.
24 // The primary insight is that much code that operates on vectors
25 // does not care about the relative order of elements in a register,
26 // so long as the correct memory order is preserved. If we have a
27 // computation where all input values are provided by lxvd2x/xxswapd,
28 // all outputs are stored using xxswapd/lxvd2x, and all intermediate
29 // computations are lane-insensitive (independent of element order),
30 // then all the xxswapd instructions associated with the loads and
31 // stores may be removed without changing observable semantics.
33 // This pass uses standard equivalence class infrastructure to create
34 // maximal webs of computations fitting the above description. Each
35 // such web is then optimized by removing its unnecessary xxswapd
38 // There are some lane-sensitive operations for which we can still
39 // permit the optimization, provided we modify those operations
40 // accordingly. Such operations are identified as using "special
41 // handling" within this module.
43 //===---------------------------------------------------------------------===//
45 #include "PPCInstrInfo.h"
47 #include "PPCInstrBuilder.h"
48 #include "PPCTargetMachine.h"
49 #include "llvm/ADT/DenseMap.h"
50 #include "llvm/ADT/EquivalenceClasses.h"
51 #include "llvm/CodeGen/MachineFunctionPass.h"
52 #include "llvm/CodeGen/MachineInstrBuilder.h"
53 #include "llvm/CodeGen/MachineRegisterInfo.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/Format.h"
56 #include "llvm/Support/raw_ostream.h"
60 #define DEBUG_TYPE "ppc-vsx-swaps"
63 void initializePPCVSXSwapRemovalPass(PassRegistry&);
68 // A PPCVSXSwapEntry is created for each machine instruction that
69 // is relevant to a vector computation.
70 struct PPCVSXSwapEntry {
71 // Pointer to the instruction.
74 // Unique ID (position in the swap vector).
77 // Attributes of this node.
78 unsigned int IsLoad : 1;
79 unsigned int IsStore : 1;
80 unsigned int IsSwap : 1;
81 unsigned int MentionsPhysVR : 1;
82 unsigned int HasImplicitSubreg : 1;
83 unsigned int IsSwappable : 1;
84 unsigned int SpecialHandling : 3;
85 unsigned int WebRejected : 1;
86 unsigned int WillRemove : 1;
99 struct PPCVSXSwapRemoval : public MachineFunctionPass {
102 const PPCInstrInfo *TII;
104 MachineRegisterInfo *MRI;
106 // Swap entries are allocated in a vector for better performance.
107 std::vector<PPCVSXSwapEntry> SwapVector;
109 // A mapping is maintained between machine instructions and
110 // their swap entries. The key is the address of the MI.
111 DenseMap<MachineInstr*, int> SwapMap;
113 // Equivalence classes are used to gather webs of related computation.
114 // Swap entries are represented by their VSEId fields.
115 EquivalenceClasses<int> *EC;
117 PPCVSXSwapRemoval() : MachineFunctionPass(ID) {
118 initializePPCVSXSwapRemovalPass(*PassRegistry::getPassRegistry());
122 // Initialize data structures.
123 void initialize(MachineFunction &MFParm);
125 // Walk the machine instructions to gather vector usage information.
126 // Return true iff vector mentions are present.
127 bool gatherVectorInstructions();
129 // Add an entry to the swap vector and swap map.
130 int addSwapEntry(MachineInstr *MI, PPCVSXSwapEntry &SwapEntry);
132 // Hunt backwards through COPY and SUBREG_TO_REG chains for a
133 // source register. VecIdx indicates the swap vector entry to
134 // mark as mentioning a physical register if the search leads
136 unsigned lookThruCopyLike(unsigned SrcReg, unsigned VecIdx);
138 // Generate equivalence classes for related computations (webs).
141 // Analyze webs and determine those that cannot be optimized.
142 void recordUnoptimizableWebs();
144 // Record which swap instructions can be safely removed.
145 void markSwapsForRemoval();
147 // Remove swaps and update other instructions requiring special
148 // handling. Return true iff any changes are made.
151 // Update instructions requiring special handling.
152 void handleSpecialSwappables(int EntryIdx);
154 // Dump a description of the entries in the swap vector.
155 void dumpSwapVector();
157 // Return true iff the given register is in the given class.
158 bool isRegInClass(unsigned Reg, const TargetRegisterClass *RC) {
159 if (TargetRegisterInfo::isVirtualRegister(Reg))
160 return RC->hasSubClassEq(MRI->getRegClass(Reg));
161 if (RC->contains(Reg))
166 // Return true iff the given register is a full vector register.
167 bool isVecReg(unsigned Reg) {
168 return (isRegInClass(Reg, &PPC::VSRCRegClass) ||
169 isRegInClass(Reg, &PPC::VRRCRegClass));
173 // Main entry point for this pass.
174 bool runOnMachineFunction(MachineFunction &MF) override {
175 // If we don't have VSX on the subtarget, don't do anything.
176 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
180 bool Changed = false;
183 if (gatherVectorInstructions()) {
185 recordUnoptimizableWebs();
186 markSwapsForRemoval();
187 Changed = removeSwaps();
190 // FIXME: See the allocation of EC in initialize().
196 // Initialize data structures for this pass. In particular, clear the
197 // swap vector and allocate the equivalence class mapping before
198 // processing each function.
199 void PPCVSXSwapRemoval::initialize(MachineFunction &MFParm) {
201 MRI = &MF->getRegInfo();
202 TII = static_cast<const PPCInstrInfo*>(MF->getSubtarget().getInstrInfo());
204 // An initial vector size of 256 appears to work well in practice.
205 // Small/medium functions with vector content tend not to incur a
206 // reallocation at this size. Three of the vector tests in
207 // projects/test-suite reallocate, which seems like a reasonable rate.
208 const int InitialVectorSize(256);
210 SwapVector.reserve(InitialVectorSize);
212 // FIXME: Currently we allocate EC each time because we don't have
213 // access to the set representation on which to call clear(). Should
214 // consider adding a clear() method to the EquivalenceClasses class.
215 EC = new EquivalenceClasses<int>;
218 // Create an entry in the swap vector for each instruction that mentions
219 // a full vector register, recording various characteristics of the
220 // instructions there.
221 bool PPCVSXSwapRemoval::gatherVectorInstructions() {
222 bool RelevantFunction = false;
224 for (MachineBasicBlock &MBB : *MF) {
225 for (MachineInstr &MI : MBB) {
227 bool RelevantInstr = false;
228 bool ImplicitSubreg = false;
230 for (const MachineOperand &MO : MI.operands()) {
233 unsigned Reg = MO.getReg();
235 RelevantInstr = true;
236 if (MO.getSubReg() != 0)
237 ImplicitSubreg = true;
245 RelevantFunction = true;
247 // Create a SwapEntry initialized to zeros, then fill in the
248 // instruction and ID fields before pushing it to the back
249 // of the swap vector.
250 PPCVSXSwapEntry SwapEntry{};
251 int VecIdx = addSwapEntry(&MI, SwapEntry);
254 SwapVector[VecIdx].HasImplicitSubreg = 1;
256 switch(MI.getOpcode()) {
258 // Unless noted otherwise, an instruction is considered
259 // safe for the optimization. There are a large number of
260 // such true-SIMD instructions (all vector math, logical,
261 // select, compare, etc.).
262 SwapVector[VecIdx].IsSwappable = 1;
265 // This is a swap if it is of the form XXPERMDI t, s, s, 2.
266 // Unfortunately, MachineCSE ignores COPY and SUBREG_TO_REG, so we
267 // can also see XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), 2,
268 // for example. We have to look through chains of COPY and
269 // SUBREG_TO_REG to find the real source value for comparison.
270 // If the real source value is a physical register, then mark the
271 // XXPERMDI as mentioning a physical register.
272 // Any other form of XXPERMDI is lane-sensitive and unsafe
273 // for the optimization.
274 if (MI.getOperand(3).getImm() == 2) {
275 unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
277 unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
279 if (trueReg1 == trueReg2)
280 SwapVector[VecIdx].IsSwap = 1;
284 // Non-permuting loads are currently unsafe. We can use special
285 // handling for this in the future. By not marking these as
286 // IsSwap, we ensure computations containing them will be rejected
288 SwapVector[VecIdx].IsLoad = 1;
292 // Permuting loads are marked as both load and swap, and are
293 // safe for optimization.
294 SwapVector[VecIdx].IsLoad = 1;
295 SwapVector[VecIdx].IsSwap = 1;
298 // Non-permuting stores are currently unsafe. We can use special
299 // handling for this in the future. By not marking these as
300 // IsSwap, we ensure computations containing them will be rejected
302 SwapVector[VecIdx].IsStore = 1;
306 // Permuting stores are marked as both store and swap, and are
307 // safe for optimization.
308 SwapVector[VecIdx].IsStore = 1;
309 SwapVector[VecIdx].IsSwap = 1;
311 case PPC::SUBREG_TO_REG:
312 // These are fine provided they are moving between full vector
313 // register classes. For example, the VRs are a subset of the
314 // VSRs, but each VR and each VSR is a full 128-bit register.
315 if (isVecReg(MI.getOperand(0).getReg()) &&
316 isVecReg(MI.getOperand(2).getReg()))
317 SwapVector[VecIdx].IsSwappable = 1;
320 // These are fine provided they are moving between full vector
322 if (isVecReg(MI.getOperand(0).getReg()) &&
323 isVecReg(MI.getOperand(1).getReg()))
324 SwapVector[VecIdx].IsSwappable = 1;
329 // Splats are lane-sensitive, but we can use special handling
330 // to adjust the source lane for the splat. This is not yet
331 // implemented. When it is, we need to uncomment the following:
332 // SwapVector[VecIdx].IsSwappable = 1;
333 SwapVector[VecIdx].SpecialHandling = SHValues::SH_SPLAT;
335 // The presence of the following lane-sensitive operations in a
336 // web will kill the optimization, at least for now. For these
337 // we do nothing, causing the optimization to fail.
338 // FIXME: Some of these could be permitted with special handling,
339 // and will be phased in as time permits.
340 // FIXME: There is no simple and maintainable way to express a set
341 // of opcodes having a common attribute in TableGen. Should this
342 // change, this is a prime candidate to use such a mechanism.
344 case PPC::EXTRACT_SUBREG:
345 case PPC::INSERT_SUBREG:
346 case PPC::COPY_TO_REGCLASS:
360 case PPC::VCIPHERLAST:
380 case PPC::VNCIPHERLAST:
401 case PPC::VSHASIGMAD:
402 case PPC::VSHASIGMAW:
427 if (RelevantFunction) {
428 DEBUG(dbgs() << "Swap vector when first built\n\n");
432 return RelevantFunction;
435 // Add an entry to the swap vector and swap map, and make a
436 // singleton equivalence class for the entry.
437 int PPCVSXSwapRemoval::addSwapEntry(MachineInstr *MI,
438 PPCVSXSwapEntry& SwapEntry) {
439 SwapEntry.VSEMI = MI;
440 SwapEntry.VSEId = SwapVector.size();
441 SwapVector.push_back(SwapEntry);
442 EC->insert(SwapEntry.VSEId);
443 SwapMap[MI] = SwapEntry.VSEId;
444 return SwapEntry.VSEId;
447 // This is used to find the "true" source register for an
448 // XXPERMDI instruction, since MachineCSE does not handle the
449 // "copy-like" operations (Copy and SubregToReg). Returns
450 // the original SrcReg unless it is the target of a copy-like
451 // operation, in which case we chain backwards through all
452 // such operations to the ultimate source register. If a
453 // physical register is encountered, we stop the search and
454 // flag the swap entry indicated by VecIdx (the original
455 // XXPERMDI) as mentioning a physical register. Similarly
456 // for implicit subregister mentions (which should never
458 unsigned PPCVSXSwapRemoval::lookThruCopyLike(unsigned SrcReg,
460 MachineInstr *MI = MRI->getVRegDef(SrcReg);
461 if (!MI->isCopyLike())
464 unsigned CopySrcReg, CopySrcSubreg;
466 CopySrcReg = MI->getOperand(1).getReg();
467 CopySrcSubreg = MI->getOperand(1).getSubReg();
469 assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike");
470 CopySrcReg = MI->getOperand(2).getReg();
471 CopySrcSubreg = MI->getOperand(2).getSubReg();
474 if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg)) {
475 SwapVector[VecIdx].MentionsPhysVR = 1;
479 if (CopySrcSubreg != 0) {
480 SwapVector[VecIdx].HasImplicitSubreg = 1;
484 return lookThruCopyLike(CopySrcReg, VecIdx);
487 // Generate equivalence classes for related computations (webs) by
488 // def-use relationships of virtual registers. Mention of a physical
489 // register terminates the generation of equivalence classes as this
490 // indicates a use of a parameter, definition of a return value, use
491 // of a value returned from a call, or definition of a parameter to a
492 // call. Computations with physical register mentions are flagged
493 // as such so their containing webs will not be optimized.
494 void PPCVSXSwapRemoval::formWebs() {
496 DEBUG(dbgs() << "\n*** Forming webs for swap removal ***\n\n");
498 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
500 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
502 DEBUG(dbgs() << "\n" << SwapVector[EntryIdx].VSEId << " ");
505 // It's sufficient to walk vector uses and join them to their unique
506 // definitions. In addition, check *all* vector register operands
507 // for physical regs.
508 for (const MachineOperand &MO : MI->operands()) {
512 unsigned Reg = MO.getReg();
516 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
517 SwapVector[EntryIdx].MentionsPhysVR = 1;
524 MachineInstr* DefMI = MRI->getVRegDef(Reg);
525 assert(SwapMap.find(DefMI) != SwapMap.end() &&
526 "Inconsistency: def of vector reg not found in swap map!");
527 int DefIdx = SwapMap[DefMI];
528 (void)EC->unionSets(SwapVector[DefIdx].VSEId,
529 SwapVector[EntryIdx].VSEId);
531 DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[DefIdx].VSEId,
532 SwapVector[EntryIdx].VSEId));
533 DEBUG(dbgs() << " Def: ");
534 DEBUG(DefMI->dump());
539 // Walk the swap vector entries looking for conditions that prevent their
540 // containing computations from being optimized. When such conditions are
541 // found, mark the representative of the computation's equivalence class
543 void PPCVSXSwapRemoval::recordUnoptimizableWebs() {
545 DEBUG(dbgs() << "\n*** Rejecting webs for swap removal ***\n\n");
547 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
548 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
550 // Reject webs containing mentions of physical registers or implicit
551 // subregs, or containing operations that we don't know how to handle
552 // in a lane-permuted region.
553 if (SwapVector[EntryIdx].MentionsPhysVR ||
554 SwapVector[EntryIdx].HasImplicitSubreg ||
555 !(SwapVector[EntryIdx].IsSwappable || SwapVector[EntryIdx].IsSwap)) {
557 SwapVector[Repr].WebRejected = 1;
560 format("Web %d rejected for physreg, subreg, or not swap[pable]\n",
562 DEBUG(dbgs() << " in " << EntryIdx << ": ");
563 DEBUG(SwapVector[EntryIdx].VSEMI->dump());
564 DEBUG(dbgs() << "\n");
567 // Reject webs than contain swapping loads that feed something other
568 // than a swap instruction.
569 else if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
570 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
571 unsigned DefReg = MI->getOperand(0).getReg();
573 // We skip debug instructions in the analysis. (Note that debug
574 // location information is still maintained by this optimization
575 // because it remains on the LXVD2X and STXVD2X instructions after
576 // the XXPERMDIs are removed.)
577 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
578 int UseIdx = SwapMap[&UseMI];
580 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad ||
581 SwapVector[UseIdx].IsStore) {
583 SwapVector[Repr].WebRejected = 1;
586 format("Web %d rejected for load not feeding swap\n", Repr));
587 DEBUG(dbgs() << " def " << EntryIdx << ": ");
589 DEBUG(dbgs() << " use " << UseIdx << ": ");
591 DEBUG(dbgs() << "\n");
595 // Reject webs than contain swapping stores that are fed by something
596 // other than a swap instruction.
597 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) {
598 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
599 unsigned UseReg = MI->getOperand(0).getReg();
600 MachineInstr *DefMI = MRI->getVRegDef(UseReg);
601 int DefIdx = SwapMap[DefMI];
603 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
604 SwapVector[DefIdx].IsStore) {
606 SwapVector[Repr].WebRejected = 1;
609 format("Web %d rejected for store not fed by swap\n", Repr));
610 DEBUG(dbgs() << " def " << DefIdx << ": ");
611 DEBUG(DefMI->dump());
612 DEBUG(dbgs() << " use " << EntryIdx << ": ");
614 DEBUG(dbgs() << "\n");
619 DEBUG(dbgs() << "Swap vector after web analysis:\n\n");
623 // Walk the swap vector entries looking for swaps fed by permuting loads
624 // and swaps that feed permuting stores. If the containing computation
625 // has not been marked rejected, mark each such swap for removal.
626 // (Removal is delayed in case optimization has disturbed the pattern,
627 // such that multiple loads feed the same swap, etc.)
628 void PPCVSXSwapRemoval::markSwapsForRemoval() {
630 DEBUG(dbgs() << "\n*** Marking swaps for removal ***\n\n");
632 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
634 if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
635 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
637 if (!SwapVector[Repr].WebRejected) {
638 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
639 unsigned DefReg = MI->getOperand(0).getReg();
641 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
642 int UseIdx = SwapMap[&UseMI];
643 SwapVector[UseIdx].WillRemove = 1;
645 DEBUG(dbgs() << "Marking swap fed by load for removal: ");
650 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) {
651 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
653 if (!SwapVector[Repr].WebRejected) {
654 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
655 unsigned UseReg = MI->getOperand(0).getReg();
656 MachineInstr *DefMI = MRI->getVRegDef(UseReg);
657 int DefIdx = SwapMap[DefMI];
658 SwapVector[DefIdx].WillRemove = 1;
660 DEBUG(dbgs() << "Marking swap feeding store for removal: ");
661 DEBUG(DefMI->dump());
664 } else if (SwapVector[EntryIdx].IsSwappable &&
665 SwapVector[EntryIdx].SpecialHandling != 0)
666 handleSpecialSwappables(EntryIdx);
670 // The identified swap entry requires special handling to allow its
671 // containing computation to be optimized. Perform that handling
673 // FIXME: This code is to be phased in with subsequent patches.
674 void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
677 // Walk the swap vector and replace each entry marked for removal with
679 bool PPCVSXSwapRemoval::removeSwaps() {
681 DEBUG(dbgs() << "\n*** Removing swaps ***\n\n");
683 bool Changed = false;
685 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
686 if (SwapVector[EntryIdx].WillRemove) {
688 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
689 MachineBasicBlock *MBB = MI->getParent();
690 BuildMI(*MBB, MI, MI->getDebugLoc(),
691 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
692 .addOperand(MI->getOperand(1));
694 DEBUG(dbgs() << format("Replaced %d with copy: ",
695 SwapVector[EntryIdx].VSEId));
698 MI->eraseFromParent();
705 // For debug purposes, dump the contents of the swap vector.
706 void PPCVSXSwapRemoval::dumpSwapVector() {
708 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
710 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
711 int ID = SwapVector[EntryIdx].VSEId;
713 DEBUG(dbgs() << format("%6d", ID));
714 DEBUG(dbgs() << format("%6d", EC->getLeaderValue(ID)));
715 DEBUG(dbgs() << format(" BB#%3d", MI->getParent()->getNumber()));
716 DEBUG(dbgs() << format(" %14s ", TII->getName(MI->getOpcode())));
718 if (SwapVector[EntryIdx].IsLoad)
719 DEBUG(dbgs() << "load ");
720 if (SwapVector[EntryIdx].IsStore)
721 DEBUG(dbgs() << "store ");
722 if (SwapVector[EntryIdx].IsSwap)
723 DEBUG(dbgs() << "swap ");
724 if (SwapVector[EntryIdx].MentionsPhysVR)
725 DEBUG(dbgs() << "physreg ");
726 if (SwapVector[EntryIdx].HasImplicitSubreg)
727 DEBUG(dbgs() << "implsubreg ");
729 if (SwapVector[EntryIdx].IsSwappable) {
730 DEBUG(dbgs() << "swappable ");
731 switch(SwapVector[EntryIdx].SpecialHandling) {
733 DEBUG(dbgs() << "special:**unknown**");
738 DEBUG(dbgs() << "special:buildvec ");
741 DEBUG(dbgs() << "special:extract ");
744 DEBUG(dbgs() << "special:insert ");
747 DEBUG(dbgs() << "special:load ");
750 DEBUG(dbgs() << "special:store ");
753 DEBUG(dbgs() << "special:splat ");
758 if (SwapVector[EntryIdx].WebRejected)
759 DEBUG(dbgs() << "rejected ");
760 if (SwapVector[EntryIdx].WillRemove)
761 DEBUG(dbgs() << "remove ");
763 DEBUG(dbgs() << "\n");
765 // For no-asserts builds.
770 DEBUG(dbgs() << "\n");
773 } // end default namespace
775 INITIALIZE_PASS_BEGIN(PPCVSXSwapRemoval, DEBUG_TYPE,
776 "PowerPC VSX Swap Removal", false, false)
777 INITIALIZE_PASS_END(PPCVSXSwapRemoval, DEBUG_TYPE,
778 "PowerPC VSX Swap Removal", false, false)
780 char PPCVSXSwapRemoval::ID = 0;
782 llvm::createPPCVSXSwapRemovalPass() { return new PPCVSXSwapRemoval(); }