1 //===-- InstSelectSimple.cpp - A simple instruction selector for PowerPC --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "isel"
12 #include "PowerPCInstrBuilder.h"
13 #include "PowerPCInstrInfo.h"
14 #include "llvm/Constants.h"
15 #include "llvm/DerivedTypes.h"
16 #include "llvm/Function.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/CodeGen/IntrinsicLowering.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/MRegisterInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/GetElementPtrTypeIterator.h"
27 #include "llvm/Support/InstVisitor.h"
28 #include "Support/Debug.h"
33 /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
34 /// PPC Representation.
37 cByte, cShort, cInt, cFP, cLong
41 /// getClass - Turn a primitive type into a "class" number which is based on the
42 /// size of the type, and whether or not it is floating point.
44 static inline TypeClass getClass(const Type *Ty) {
45 switch (Ty->getTypeID()) {
47 case Type::UByteTyID: return cByte; // Byte operands are class #0
49 case Type::UShortTyID: return cShort; // Short operands are class #1
52 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
55 case Type::DoubleTyID: return cFP; // Floating Point is #3
58 case Type::ULongTyID: return cLong; // Longs are class #4
60 assert(0 && "Invalid type to getClass!");
61 return cByte; // not reached
65 // getClassB - Just like getClass, but treat boolean values as ints.
66 static inline TypeClass getClassB(const Type *Ty) {
67 if (Ty == Type::BoolTy) return cInt;
72 struct ISel : public FunctionPass, InstVisitor<ISel> {
74 MachineFunction *F; // The function we are compiling into
75 MachineBasicBlock *BB; // The current MBB we are compiling
76 int VarArgsFrameIndex; // FrameIndex for start of varargs area
77 int ReturnAddressIndex; // FrameIndex for the return address
79 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
81 // MBBMap - Mapping between LLVM BB -> Machine BB
82 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
84 // AllocaMap - Mapping from fixed sized alloca instructions to the
85 // FrameIndex for the alloca.
86 std::map<AllocaInst*, unsigned> AllocaMap;
88 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
90 /// runOnFunction - Top level implementation of instruction selection for
91 /// the entire function.
93 bool runOnFunction(Function &Fn) {
94 // First pass over the function, lower any unknown intrinsic functions
95 // with the IntrinsicLowering class.
96 LowerUnknownIntrinsicFunctionCalls(Fn);
98 F = &MachineFunction::construct(&Fn, TM);
100 // Create all of the machine basic blocks for the function...
101 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
102 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
106 // Set up a frame object for the return address. This is used by the
107 // llvm.returnaddress & llvm.frameaddress intrinisics.
108 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
110 // Copy incoming arguments off of the stack...
111 LoadArgumentsToVirtualRegs(Fn);
113 // Instruction select everything except PHI nodes
116 // Select the PHI nodes
123 // We always build a machine code representation for the function
127 virtual const char *getPassName() const {
128 return "PowerPC Simple Instruction Selection";
131 /// visitBasicBlock - This method is called when we are visiting a new basic
132 /// block. This simply creates a new MachineBasicBlock to emit code into
133 /// and adds it to the current MachineFunction. Subsequent visit* for
134 /// instructions will be invoked for all instructions in the basic block.
136 void visitBasicBlock(BasicBlock &LLVM_BB) {
137 BB = MBBMap[&LLVM_BB];
140 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
141 /// function, lowering any calls to unknown intrinsic functions into the
142 /// equivalent LLVM code.
144 void LowerUnknownIntrinsicFunctionCalls(Function &F);
146 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
147 /// from the stack into virtual registers.
149 void LoadArgumentsToVirtualRegs(Function &F);
151 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
152 /// because we have to generate our sources into the source basic blocks,
153 /// not the current one.
155 void SelectPHINodes();
157 // Visitation methods for various instructions. These methods simply emit
158 // fixed PowerPC code for each instruction.
160 // Control flow operators
161 void visitReturnInst(ReturnInst &RI);
162 void visitBranchInst(BranchInst &BI);
168 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
169 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
171 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
172 const std::vector<ValueRecord> &Args);
173 void visitCallInst(CallInst &I);
174 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
176 // Arithmetic operators
177 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
178 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
179 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
180 void visitMul(BinaryOperator &B);
182 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
183 void visitRem(BinaryOperator &B) { visitDivRem(B); }
184 void visitDivRem(BinaryOperator &B);
187 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
188 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
189 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
191 // Comparison operators...
192 void visitSetCondInst(SetCondInst &I);
193 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
194 MachineBasicBlock *MBB,
195 MachineBasicBlock::iterator MBBI);
196 void visitSelectInst(SelectInst &SI);
199 // Memory Instructions
200 void visitLoadInst(LoadInst &I);
201 void visitStoreInst(StoreInst &I);
202 void visitGetElementPtrInst(GetElementPtrInst &I);
203 void visitAllocaInst(AllocaInst &I);
204 void visitMallocInst(MallocInst &I);
205 void visitFreeInst(FreeInst &I);
208 void visitShiftInst(ShiftInst &I);
209 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
210 void visitCastInst(CastInst &I);
211 void visitVANextInst(VANextInst &I);
212 void visitVAArgInst(VAArgInst &I);
214 void visitInstruction(Instruction &I) {
215 std::cerr << "Cannot instruction select: " << I;
219 /// promote32 - Make a value 32-bits wide, and put it somewhere.
221 void promote32(unsigned targetReg, const ValueRecord &VR);
223 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
224 /// constant expression GEP support.
226 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
227 Value *Src, User::op_iterator IdxBegin,
228 User::op_iterator IdxEnd, unsigned TargetReg);
230 /// emitCastOperation - Common code shared between visitCastInst and
231 /// constant expression cast support.
233 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
234 Value *Src, const Type *DestTy, unsigned TargetReg);
236 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
237 /// and constant expression support.
239 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
240 MachineBasicBlock::iterator IP,
241 Value *Op0, Value *Op1,
242 unsigned OperatorClass, unsigned TargetReg);
244 /// emitBinaryFPOperation - This method handles emission of floating point
245 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
246 void emitBinaryFPOperation(MachineBasicBlock *BB,
247 MachineBasicBlock::iterator IP,
248 Value *Op0, Value *Op1,
249 unsigned OperatorClass, unsigned TargetReg);
251 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
252 Value *Op0, Value *Op1, unsigned TargetReg);
254 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
255 unsigned DestReg, const Type *DestTy,
256 unsigned Op0Reg, unsigned Op1Reg);
257 void doMultiplyConst(MachineBasicBlock *MBB,
258 MachineBasicBlock::iterator MBBI,
259 unsigned DestReg, const Type *DestTy,
260 unsigned Op0Reg, unsigned Op1Val);
262 void emitDivRemOperation(MachineBasicBlock *BB,
263 MachineBasicBlock::iterator IP,
264 Value *Op0, Value *Op1, bool isDiv,
267 /// emitSetCCOperation - Common code shared between visitSetCondInst and
268 /// constant expression support.
270 void emitSetCCOperation(MachineBasicBlock *BB,
271 MachineBasicBlock::iterator IP,
272 Value *Op0, Value *Op1, unsigned Opcode,
275 /// emitShiftOperation - Common code shared between visitShiftInst and
276 /// constant expression support.
278 void emitShiftOperation(MachineBasicBlock *MBB,
279 MachineBasicBlock::iterator IP,
280 Value *Op, Value *ShiftAmount, bool isLeftShift,
281 const Type *ResultTy, unsigned DestReg);
283 /// emitSelectOperation - Common code shared between visitSelectInst and the
284 /// constant expression support.
285 void emitSelectOperation(MachineBasicBlock *MBB,
286 MachineBasicBlock::iterator IP,
287 Value *Cond, Value *TrueVal, Value *FalseVal,
290 /// copyConstantToRegister - Output the instructions required to put the
291 /// specified constant into the specified register.
293 void copyConstantToRegister(MachineBasicBlock *MBB,
294 MachineBasicBlock::iterator MBBI,
295 Constant *C, unsigned Reg);
297 void emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
298 unsigned LHS, unsigned RHS);
300 /// makeAnotherReg - This method returns the next register number we haven't
303 /// Long values are handled somewhat specially. They are always allocated
304 /// as pairs of 32 bit integer values. The register number returned is the
305 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
306 /// of the long value.
308 unsigned makeAnotherReg(const Type *Ty) {
309 assert(dynamic_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()) &&
310 "Current target doesn't have PPC reg info??");
311 const PowerPCRegisterInfo *MRI =
312 static_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo());
313 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
314 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
315 // Create the lower part
316 F->getSSARegMap()->createVirtualRegister(RC);
317 // Create the upper part.
318 return F->getSSARegMap()->createVirtualRegister(RC)-1;
321 // Add the mapping of regnumber => reg class to MachineFunction
322 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
323 return F->getSSARegMap()->createVirtualRegister(RC);
326 /// getReg - This method turns an LLVM value into a register number.
328 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
329 unsigned getReg(Value *V) {
330 // Just append to the end of the current bb.
331 MachineBasicBlock::iterator It = BB->end();
332 return getReg(V, BB, It);
334 unsigned getReg(Value *V, MachineBasicBlock *MBB,
335 MachineBasicBlock::iterator IPt);
337 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
338 /// that is to be statically allocated with the initial stack frame
340 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
344 /// dyn_castFixedAlloca - If the specified value is a fixed size alloca
345 /// instruction in the entry block, return it. Otherwise, return a null
347 static AllocaInst *dyn_castFixedAlloca(Value *V) {
348 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
349 BasicBlock *BB = AI->getParent();
350 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
356 /// getReg - This method turns an LLVM value into a register number.
358 unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
359 MachineBasicBlock::iterator IPt) {
360 // If this operand is a constant, emit the code to copy the constant into
361 // the register here...
363 if (Constant *C = dyn_cast<Constant>(V)) {
364 unsigned Reg = makeAnotherReg(V->getType());
365 copyConstantToRegister(MBB, IPt, C, Reg);
367 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
368 // GV is located at PC + distance
369 unsigned CurPC = makeAnotherReg(Type::IntTy);
370 unsigned Reg1 = makeAnotherReg(V->getType());
371 unsigned Reg2 = makeAnotherReg(V->getType());
372 // Move PC to destination reg
373 BuildMI(*MBB, IPt, PPC32::MovePCtoLR, 0, CurPC);
374 // Move value at PC + distance into return reg
375 BuildMI(*MBB, IPt, PPC32::LOADHiAddr, 2, Reg1).addReg(CurPC)
376 .addGlobalAddress(GV);
377 BuildMI(*MBB, IPt, PPC32::LOADLoAddr, 2, Reg2).addReg(Reg1)
378 .addGlobalAddress(GV);
380 } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
381 // Do not emit noop casts at all.
382 if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
383 return getReg(CI->getOperand(0), MBB, IPt);
384 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
385 unsigned Reg = makeAnotherReg(V->getType());
386 unsigned FI = getFixedSizedAllocaFI(AI);
387 addFrameReference(BuildMI(*MBB, IPt, PPC32::ADDI, 2, Reg), FI, 0, false);
391 unsigned &Reg = RegMap[V];
393 Reg = makeAnotherReg(V->getType());
400 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
401 /// that is to be statically allocated with the initial stack frame
403 unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
404 // Already computed this?
405 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
406 if (I != AllocaMap.end() && I->first == AI) return I->second;
408 const Type *Ty = AI->getAllocatedType();
409 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
410 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
411 TySize *= CUI->getValue(); // Get total allocated size...
412 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
414 // Create a new stack object using the frame manager...
415 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
416 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
421 /// copyConstantToRegister - Output the instructions required to put the
422 /// specified constant into the specified register.
424 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
425 MachineBasicBlock::iterator IP,
426 Constant *C, unsigned R) {
427 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
429 switch (CE->getOpcode()) {
430 case Instruction::GetElementPtr:
431 emitGEPOperation(MBB, IP, CE->getOperand(0),
432 CE->op_begin()+1, CE->op_end(), R);
434 case Instruction::Cast:
435 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
438 case Instruction::Xor: ++Class; // FALL THROUGH
439 case Instruction::Or: ++Class; // FALL THROUGH
440 case Instruction::And: ++Class; // FALL THROUGH
441 case Instruction::Sub: ++Class; // FALL THROUGH
442 case Instruction::Add:
443 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
447 case Instruction::Mul:
448 emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
451 case Instruction::Div:
452 case Instruction::Rem:
453 emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
454 CE->getOpcode() == Instruction::Div, R);
457 case Instruction::SetNE:
458 case Instruction::SetEQ:
459 case Instruction::SetLT:
460 case Instruction::SetGT:
461 case Instruction::SetLE:
462 case Instruction::SetGE:
463 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
467 case Instruction::Shl:
468 case Instruction::Shr:
469 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
470 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
473 case Instruction::Select:
474 emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
475 CE->getOperand(2), R);
479 std::cerr << "Offending expr: " << C << "\n";
480 assert(0 && "Constant expression not yet handled!\n");
484 if (C->getType()->isIntegral()) {
485 unsigned Class = getClassB(C->getType());
487 if (Class == cLong) {
488 // Copy the value into the register pair.
489 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
490 unsigned hiTmp = makeAnotherReg(Type::IntTy);
491 unsigned loTmp = makeAnotherReg(Type::IntTy);
492 BuildMI(*MBB, IP, PPC32::ADDIS, 2, loTmp).addReg(PPC32::R0)
494 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(loTmp)
495 .addImm((Val >> 32) & 0xFFFF);
496 BuildMI(*MBB, IP, PPC32::ADDIS, 2, hiTmp).addReg(PPC32::R0)
497 .addImm((Val >> 16) & 0xFFFF);
498 BuildMI(*MBB, IP, PPC32::ORI, 2, R+1).addReg(hiTmp).addImm(Val & 0xFFFF);
502 assert(Class <= cInt && "Type not handled yet!");
504 if (C->getType() == Type::BoolTy) {
505 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0)
506 .addImm(C == ConstantBool::True);
507 } else if (Class == cByte || Class == cShort) {
508 ConstantInt *CI = cast<ConstantInt>(C);
509 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0)
510 .addImm(CI->getRawValue());
512 ConstantInt *CI = cast<ConstantInt>(C);
513 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
514 if (TheVal < 32768 && TheVal >= -32768) {
515 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0)
516 .addImm(CI->getRawValue());
518 unsigned TmpReg = makeAnotherReg(Type::IntTy);
519 BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0)
520 .addImm(CI->getRawValue() >> 16);
521 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(TmpReg)
522 .addImm(CI->getRawValue() & 0xFFFF);
525 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
526 // We need to spill the constant to memory...
527 MachineConstantPool *CP = F->getConstantPool();
528 unsigned CPI = CP->getConstantPoolIndex(CFP);
529 const Type *Ty = CFP->getType();
531 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
532 unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
533 addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 2, R), CPI);
534 } else if (isa<ConstantPointerNull>(C)) {
535 // Copy zero (null pointer) to the register.
536 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(0);
537 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
538 BuildMI(*MBB, IP, PPC32::ADDIS, 2, R).addReg(PPC32::R0)
539 .addGlobalAddress(CPR->getValue());
540 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(PPC32::R0)
541 .addGlobalAddress(CPR->getValue());
543 std::cerr << "Offending constant: " << C << "\n";
544 assert(0 && "Type not handled yet!");
548 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
549 /// the stack into virtual registers.
551 /// FIXME: When we can calculate which args are coming in via registers
552 /// source them from there instead.
553 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
554 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
555 unsigned GPR_remaining = 8;
556 unsigned FPR_remaining = 13;
557 unsigned GPR_idx = 3;
558 unsigned FPR_idx = 1;
560 MachineFrameInfo *MFI = F->getFrameInfo();
562 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
563 bool ArgLive = !I->use_empty();
564 unsigned Reg = ArgLive ? getReg(*I) : 0;
565 int FI; // Frame object index
567 switch (getClassB(I->getType())) {
570 FI = MFI->CreateFixedObject(1, ArgOffset);
571 if (GPR_remaining > 0) {
572 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx)
573 .addReg(PPC32::R0+GPR_idx);
575 addFrameReference(BuildMI(BB, PPC32::LBZ, 2, Reg), FI);
581 FI = MFI->CreateFixedObject(2, ArgOffset);
582 if (GPR_remaining > 0) {
583 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx)
584 .addReg(PPC32::R0+GPR_idx);
586 addFrameReference(BuildMI(BB, PPC32::LHZ, 2, Reg), FI);
592 FI = MFI->CreateFixedObject(4, ArgOffset);
593 if (GPR_remaining > 0) {
594 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx)
595 .addReg(PPC32::R0+GPR_idx);
597 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
603 FI = MFI->CreateFixedObject(8, ArgOffset);
604 if (GPR_remaining > 1) {
605 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx)
606 .addReg(PPC32::R0+GPR_idx);
607 BuildMI(BB, PPC32::OR, 2, Reg+1).addReg(PPC32::R0+GPR_idx+1)
608 .addReg(PPC32::R0+GPR_idx+1);
610 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
611 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg+1), FI, 4);
614 ArgOffset += 4; // longs require 4 additional bytes
615 if (GPR_remaining > 1) {
616 GPR_remaining--; // uses up 2 GPRs
623 if (I->getType() == Type::FloatTy) {
625 FI = MFI->CreateFixedObject(4, ArgOffset);
628 FI = MFI->CreateFixedObject(8, ArgOffset);
630 if (FPR_remaining > 0) {
631 BuildMI(BB, PPC32::FMR, 1, Reg).addReg(PPC32::F0+FPR_idx);
635 addFrameReference(BuildMI(BB, Opcode, 2, Reg), FI);
638 if (I->getType() == Type::DoubleTy) {
639 ArgOffset += 4; // doubles require 4 additional bytes
640 if (GPR_remaining > 0) {
641 GPR_remaining--; // uses up 2 GPRs
647 assert(0 && "Unhandled argument type!");
649 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
650 if (GPR_remaining > 0) {
651 GPR_remaining--; // uses up 2 GPRs
656 // If the function takes variable number of arguments, add a frame offset for
657 // the start of the first vararg value... this is used to expand
659 if (Fn.getFunctionType()->isVarArg())
660 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
664 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
665 /// because we have to generate our sources into the source basic blocks, not
668 void ISel::SelectPHINodes() {
669 const TargetInstrInfo &TII = *TM.getInstrInfo();
670 const Function &LF = *F->getFunction(); // The LLVM function...
671 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
672 const BasicBlock *BB = I;
673 MachineBasicBlock &MBB = *MBBMap[I];
675 // Loop over all of the PHI nodes in the LLVM basic block...
676 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
677 for (BasicBlock::const_iterator I = BB->begin();
678 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
680 // Create a new machine instr PHI node, and insert it.
681 unsigned PHIReg = getReg(*PN);
682 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
683 PPC32::PHI, PN->getNumOperands(), PHIReg);
685 MachineInstr *LongPhiMI = 0;
686 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
687 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
688 PPC32::PHI, PN->getNumOperands(), PHIReg+1);
690 // PHIValues - Map of blocks to incoming virtual registers. We use this
691 // so that we only initialize one incoming value for a particular block,
692 // even if the block has multiple entries in the PHI node.
694 std::map<MachineBasicBlock*, unsigned> PHIValues;
696 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
697 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
699 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
700 PHIValues.lower_bound(PredMBB);
702 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
703 // We already inserted an initialization of the register for this
704 // predecessor. Recycle it.
705 ValReg = EntryIt->second;
708 // Get the incoming value into a virtual register.
710 Value *Val = PN->getIncomingValue(i);
712 // If this is a constant or GlobalValue, we may have to insert code
713 // into the basic block to compute it into a virtual register.
714 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
715 isa<GlobalValue>(Val)) {
716 // Simple constants get emitted at the end of the basic block,
717 // before any terminator instructions. We "know" that the code to
718 // move a constant into a register will never clobber any flags.
719 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
721 // Because we don't want to clobber any values which might be in
722 // physical registers with the computation of this constant (which
723 // might be arbitrarily complex if it is a constant expression),
724 // just insert the computation at the top of the basic block.
725 MachineBasicBlock::iterator PI = PredMBB->begin();
727 // Skip over any PHI nodes though!
728 while (PI != PredMBB->end() && PI->getOpcode() == PPC32::PHI)
731 ValReg = getReg(Val, PredMBB, PI);
734 // Remember that we inserted a value for this PHI for this predecessor
735 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
738 PhiMI->addRegOperand(ValReg);
739 PhiMI->addMachineBasicBlockOperand(PredMBB);
741 LongPhiMI->addRegOperand(ValReg+1);
742 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
746 // Now that we emitted all of the incoming values for the PHI node, make
747 // sure to reposition the InsertPoint after the PHI that we just added.
748 // This is needed because we might have inserted a constant into this
749 // block, right after the PHI's which is before the old insert point!
750 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
757 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
758 // it into the conditional branch or select instruction which is the only user
759 // of the cc instruction. This is the case if the conditional branch is the
760 // only user of the setcc, and if the setcc is in the same basic block as the
761 // conditional branch. We also don't handle long arguments below, so we reject
762 // them here as well.
764 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
765 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
766 if (SCI->hasOneUse()) {
767 Instruction *User = cast<Instruction>(SCI->use_back());
768 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
769 SCI->getParent() == User->getParent() &&
770 (getClassB(SCI->getOperand(0)->getType()) != cLong ||
771 SCI->getOpcode() == Instruction::SetEQ ||
772 SCI->getOpcode() == Instruction::SetNE))
778 // Return a fixed numbering for setcc instructions which does not depend on the
779 // order of the opcodes.
781 static unsigned getSetCCNumber(unsigned Opcode) {
783 default: assert(0 && "Unknown setcc instruction!");
784 case Instruction::SetEQ: return 0;
785 case Instruction::SetNE: return 1;
786 case Instruction::SetLT: return 2;
787 case Instruction::SetGE: return 3;
788 case Instruction::SetGT: return 4;
789 case Instruction::SetLE: return 5;
793 /// emitUCOM - emits an unordered FP compare.
794 void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
795 unsigned LHS, unsigned RHS) {
796 BuildMI(*MBB, IP, PPC32::FCMPU, 2, PPC32::CR0).addReg(LHS).addReg(RHS);
799 // EmitComparison - This function emits a comparison of the two operands,
800 // returning the extended setcc code to use.
801 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
802 MachineBasicBlock *MBB,
803 MachineBasicBlock::iterator IP) {
804 // The arguments are already supposed to be of the same type.
805 const Type *CompTy = Op0->getType();
806 unsigned Class = getClassB(CompTy);
807 unsigned Op0r = getReg(Op0, MBB, IP);
809 // Special case handling of: cmp R, i
810 if (isa<ConstantPointerNull>(Op1)) {
811 BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
812 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
813 if (Class == cByte || Class == cShort || Class == cInt) {
814 unsigned Op1v = CI->getRawValue();
816 // Mask off any upper bits of the constant, if there are any...
817 Op1v &= (1ULL << (8 << Class)) - 1;
819 // Compare immediate or promote to reg?
821 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMPI : PPC32::CMPLI, 3,
822 PPC32::CR0).addImm(0).addReg(Op0r).addImm(Op1v);
824 unsigned Op1r = getReg(Op1, MBB, IP);
825 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 3,
826 PPC32::CR0).addImm(0).addReg(Op0r).addReg(Op1r);
830 assert(Class == cLong && "Unknown integer class!");
831 unsigned LowCst = CI->getRawValue();
832 unsigned HiCst = CI->getRawValue() >> 32;
833 if (OpNum < 2) { // seteq, setne
834 unsigned LoTmp = Op0r;
836 unsigned LoLow = makeAnotherReg(Type::IntTy);
837 unsigned LoTmp = makeAnotherReg(Type::IntTy);
838 BuildMI(*MBB, IP, PPC32::XORI, 2, LoLow).addReg(Op0r).addImm(LowCst);
839 BuildMI(*MBB, IP, PPC32::XORIS, 2, LoTmp).addReg(LoLow)
840 .addImm(LowCst >> 16);
842 unsigned HiTmp = Op0r+1;
844 unsigned HiLow = makeAnotherReg(Type::IntTy);
845 unsigned HiTmp = makeAnotherReg(Type::IntTy);
846 BuildMI(*MBB, IP, PPC32::XORI, 2, HiLow).addReg(Op0r+1).addImm(HiCst);
847 BuildMI(*MBB, IP, PPC32::XORIS, 2, HiTmp).addReg(HiLow)
848 .addImm(HiCst >> 16);
850 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
851 BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
852 //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
855 // Emit a sequence of code which compares the high and low parts once
856 // each, then uses a conditional move to handle the overflow case. For
857 // example, a setlt for long would generate code like this:
859 // AL = lo(op1) < lo(op2) // Always unsigned comparison
860 // BL = hi(op1) < hi(op2) // Signedness depends on operands
861 // dest = hi(op1) == hi(op2) ? BL : AL;
864 // FIXME: Not Yet Implemented
865 std::cerr << "EmitComparison unimplemented: Opnum >= 2\n";
872 unsigned Op1r = getReg(Op1, MBB, IP);
874 default: assert(0 && "Unknown type class!");
878 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 2,
879 PPC32::CR0).addReg(Op0r).addReg(Op1r);
882 emitUCOM(MBB, IP, Op0r, Op1r);
886 if (OpNum < 2) { // seteq, setne
887 unsigned LoTmp = makeAnotherReg(Type::IntTy);
888 unsigned HiTmp = makeAnotherReg(Type::IntTy);
889 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
890 BuildMI(*MBB, IP, PPC32::XOR, 2, LoTmp).addReg(Op0r).addReg(Op1r);
891 BuildMI(*MBB, IP, PPC32::XOR, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
892 BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
893 //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
894 break; // Allow the sete or setne to be generated from flags set by OR
896 // Emit a sequence of code which compares the high and low parts once
897 // each, then uses a conditional move to handle the overflow case. For
898 // example, a setlt for long would generate code like this:
900 // AL = lo(op1) < lo(op2) // Signedness depends on operands
901 // BL = hi(op1) < hi(op2) // Always unsigned comparison
902 // dest = hi(op1) == hi(op2) ? BL : AL;
905 // FIXME: Not Yet Implemented
906 std::cerr << "EmitComparison (cLong) unimplemented: Opnum >= 2\n";
914 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
915 /// register, then move it to wherever the result should be.
917 void ISel::visitSetCondInst(SetCondInst &I) {
918 if (canFoldSetCCIntoBranchOrSelect(&I))
919 return; // Fold this into a branch or select.
921 unsigned DestReg = getReg(I);
922 MachineBasicBlock::iterator MII = BB->end();
923 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
927 /// emitSetCCOperation - Common code shared between visitSetCondInst and
928 /// constant expression support.
930 /// FIXME: this is wrong. we should figure out a way to guarantee
931 /// TargetReg is a CR and then make it a no-op
932 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
933 MachineBasicBlock::iterator IP,
934 Value *Op0, Value *Op1, unsigned Opcode,
935 unsigned TargetReg) {
936 unsigned OpNum = getSetCCNumber(Opcode);
937 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
939 // The value is already in CR0 at this point, do nothing.
943 void ISel::visitSelectInst(SelectInst &SI) {
944 unsigned DestReg = getReg(SI);
945 MachineBasicBlock::iterator MII = BB->end();
946 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
947 SI.getFalseValue(), DestReg);
950 /// emitSelect - Common code shared between visitSelectInst and the constant
951 /// expression support.
952 /// FIXME: this is most likely broken in one or more ways. Namely, PowerPC has
953 /// no select instruction. FSEL only works for comparisons against zero.
954 void ISel::emitSelectOperation(MachineBasicBlock *MBB,
955 MachineBasicBlock::iterator IP,
956 Value *Cond, Value *TrueVal, Value *FalseVal,
958 unsigned SelectClass = getClassB(TrueVal->getType());
960 unsigned TrueReg = getReg(TrueVal, MBB, IP);
961 unsigned FalseReg = getReg(FalseVal, MBB, IP);
963 if (TrueReg == FalseReg) {
964 if (SelectClass == cFP) {
965 BuildMI(*MBB, IP, PPC32::FMR, 1, DestReg).addReg(TrueReg);
967 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TrueReg).addReg(TrueReg);
970 if (SelectClass == cLong)
971 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TrueReg+1)
976 unsigned CondReg = getReg(Cond, MBB, IP);
977 unsigned numZeros = makeAnotherReg(Type::IntTy);
978 unsigned falseHi = makeAnotherReg(Type::IntTy);
979 unsigned falseAll = makeAnotherReg(Type::IntTy);
980 unsigned trueAll = makeAnotherReg(Type::IntTy);
981 unsigned Temp1 = makeAnotherReg(Type::IntTy);
982 unsigned Temp2 = makeAnotherReg(Type::IntTy);
984 BuildMI(*MBB, IP, PPC32::CNTLZW, 1, numZeros).addReg(CondReg);
985 BuildMI(*MBB, IP, PPC32::RLWINM, 4, falseHi).addReg(numZeros).addImm(26)
986 .addImm(0).addImm(0);
987 BuildMI(*MBB, IP, PPC32::SRAWI, 2, falseAll).addReg(falseHi).addImm(31);
988 BuildMI(*MBB, IP, PPC32::NOR, 2, trueAll).addReg(falseAll).addReg(falseAll);
989 BuildMI(*MBB, IP, PPC32::AND, 2, Temp1).addReg(TrueReg).addReg(trueAll);
990 BuildMI(*MBB, IP, PPC32::AND, 2, Temp2).addReg(FalseReg).addReg(falseAll);
991 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Temp1).addReg(Temp2);
993 if (SelectClass == cLong) {
994 unsigned Temp3 = makeAnotherReg(Type::IntTy);
995 unsigned Temp4 = makeAnotherReg(Type::IntTy);
996 BuildMI(*MBB, IP, PPC32::AND, 2, Temp3).addReg(TrueReg+1).addReg(trueAll);
997 BuildMI(*MBB, IP, PPC32::AND, 2, Temp4).addReg(FalseReg+1).addReg(falseAll);
998 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(Temp3).addReg(Temp4);
1006 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1007 /// operand, in the specified target register.
1009 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1010 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
1012 Value *Val = VR.Val;
1013 const Type *Ty = VR.Ty;
1015 if (Constant *C = dyn_cast<Constant>(Val)) {
1016 Val = ConstantExpr::getCast(C, Type::IntTy);
1020 // If this is a simple constant, just emit a load directly to avoid the copy
1021 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1022 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1024 if (TheVal < 32768 && TheVal >= -32768) {
1025 BuildMI(BB, PPC32::ADDI, 2, targetReg).addReg(PPC32::R0).addImm(TheVal);
1027 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1028 BuildMI(BB, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0)
1029 .addImm(TheVal >> 16);
1030 BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(TmpReg)
1031 .addImm(TheVal & 0xFFFF);
1037 // Make sure we have the register number for this value...
1038 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1040 switch (getClassB(Ty)) {
1042 // Extend value into target register (8->32)
1044 BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1045 .addZImm(24).addZImm(31);
1047 BuildMI(BB, PPC32::EXTSB, 1, targetReg).addReg(Reg);
1050 // Extend value into target register (16->32)
1052 BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1053 .addZImm(16).addZImm(31);
1055 BuildMI(BB, PPC32::EXTSH, 1, targetReg).addReg(Reg);
1058 // Move value into target register (32->32)
1059 BuildMI(BB, PPC32::OR, 2, targetReg).addReg(Reg).addReg(Reg);
1062 assert(0 && "Unpromotable operand class in promote32");
1066 /// visitReturnInst - implemented with BLR
1068 void ISel::visitReturnInst(ReturnInst &I) {
1069 // Only do the processing if this is a non-void return
1070 if (I.getNumOperands() > 0) {
1071 Value *RetVal = I.getOperand(0);
1072 switch (getClassB(RetVal->getType())) {
1073 case cByte: // integral return values: extend or move into r3 and return
1076 promote32(PPC32::R3, ValueRecord(RetVal));
1078 case cFP: { // Floats & Doubles: Return in f1
1079 unsigned RetReg = getReg(RetVal);
1080 BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
1084 unsigned RetReg = getReg(RetVal);
1085 BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
1086 BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
1090 visitInstruction(I);
1093 BuildMI(BB, PPC32::BLR, 1).addImm(0);
1096 // getBlockAfter - Return the basic block which occurs lexically after the
1098 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1099 Function::iterator I = BB; ++I; // Get iterator to next block
1100 return I != BB->getParent()->end() ? &*I : 0;
1103 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1104 /// that since code layout is frozen at this point, that if we are trying to
1105 /// jump to a block that is the immediate successor of the current block, we can
1106 /// just make a fall-through (but we don't currently).
1108 void ISel::visitBranchInst(BranchInst &BI) {
1109 // Update machine-CFG edges
1110 BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
1111 if (BI.isConditional())
1112 BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
1114 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1116 if (!BI.isConditional()) { // Unconditional branch?
1117 if (BI.getSuccessor(0) != NextBB)
1118 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1122 // See if we can fold the setcc into the branch itself...
1123 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1125 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1126 // computed some other way...
1127 unsigned condReg = getReg(BI.getCondition());
1128 BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(condReg)
1130 if (BI.getSuccessor(1) == NextBB) {
1131 if (BI.getSuccessor(0) != NextBB)
1132 BuildMI(BB, PPC32::BC, 3).addImm(4).addImm(2)
1133 .addMBB(MBBMap[BI.getSuccessor(0)]);
1135 BuildMI(BB, PPC32::BC, 3).addImm(12).addImm(2)
1136 .addMBB(MBBMap[BI.getSuccessor(1)]);
1138 if (BI.getSuccessor(0) != NextBB)
1139 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1144 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1145 MachineBasicBlock::iterator MII = BB->end();
1146 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1148 const Type *CompTy = SCI->getOperand(0)->getType();
1149 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1151 static const unsigned BITab[6] = { 2, 2, 0, 0, 1, 1 };
1152 unsigned BO_true = (OpNum % 2 == 0) ? 12 : 4;
1153 unsigned BO_false = (OpNum % 2 == 0) ? 4 : 12;
1154 unsigned BIval = BITab[0];
1156 if (BI.getSuccessor(0) != NextBB) {
1157 BuildMI(BB, PPC32::BC, 3).addImm(BO_true).addImm(BIval)
1158 .addMBB(MBBMap[BI.getSuccessor(0)]);
1159 if (BI.getSuccessor(1) != NextBB)
1160 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1162 // Change to the inverse condition...
1163 if (BI.getSuccessor(1) != NextBB) {
1164 BuildMI(BB, PPC32::BC, 3).addImm(BO_false).addImm(BIval)
1165 .addMBB(MBBMap[BI.getSuccessor(1)]);
1171 /// doCall - This emits an abstract call instruction, setting up the arguments
1172 /// and the return value as appropriate. For the actual function call itself,
1173 /// it inserts the specified CallMI instruction into the stream.
1175 /// FIXME: See Documentation at the following URL for "correct" behavior
1176 /// <http://developer.apple.com/documentation/DeveloperTools/Conceptual/MachORuntime/2rt_powerpc_abi/chapter_9_section_5.html>
1177 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1178 const std::vector<ValueRecord> &Args) {
1179 // Count how many bytes are to be pushed on the stack...
1180 unsigned NumBytes = 0;
1182 if (!Args.empty()) {
1183 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1184 switch (getClassB(Args[i].Ty)) {
1185 case cByte: case cShort: case cInt:
1186 NumBytes += 4; break;
1188 NumBytes += 8; break;
1190 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1192 default: assert(0 && "Unknown class!");
1195 // Adjust the stack pointer for the new arguments...
1196 BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1198 // Arguments go on the stack in reverse order, as specified by the ABI.
1199 unsigned ArgOffset = 0;
1200 int GPR_remaining = 8, FPR_remaining = 8;
1202 PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
1203 PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
1206 PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4,
1207 PPC32::F5, PPC32::F6, PPC32::F7, PPC32::F8
1209 unsigned GPR_idx = 0, FPR_idx = 0;
1211 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1213 switch (getClassB(Args[i].Ty)) {
1216 // Promote arg to 32 bits wide into a temporary register...
1217 ArgReg = makeAnotherReg(Type::UIntTy);
1218 promote32(ArgReg, Args[i]);
1221 if (GPR_remaining > 0) {
1222 BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1225 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
1230 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1233 if (GPR_remaining > 0) {
1234 BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1237 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
1242 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1245 if (GPR_remaining > 1) {
1246 BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1248 BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx + 1]).addReg(ArgReg+1)
1251 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
1253 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg+1).addImm(ArgOffset+4)
1257 ArgOffset += 4; // 8 byte entry, not 4.
1258 GPR_remaining -= 1; // uses up 2 GPRs
1262 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1263 if (Args[i].Ty == Type::FloatTy) {
1265 if (FPR_remaining > 0) {
1266 BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1270 BuildMI(BB, PPC32::STFS, 3).addReg(ArgReg).addImm(ArgOffset)
1274 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1276 if (FPR_remaining > 0) {
1277 BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1281 BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset)
1285 ArgOffset += 4; // 8 byte entry, not 4.
1286 GPR_remaining--; // uses up 2 GPRs
1291 default: assert(0 && "Unknown class!");
1298 BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(0);
1301 BB->push_back(CallMI);
1303 BuildMI(BB, PPC32::ADJCALLSTACKUP, 1).addImm(NumBytes);
1305 // If there is a return value, scavenge the result from the location the call
1308 if (Ret.Ty != Type::VoidTy) {
1309 unsigned DestClass = getClassB(Ret.Ty);
1310 switch (DestClass) {
1314 // Integral results are in r3
1315 BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
1317 case cFP: // Floating-point return values live in f1
1318 BuildMI(BB, PPC32::FMR, 1, Ret.Reg).addReg(PPC32::F1);
1320 case cLong: // Long values are in r3:r4
1321 BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
1322 BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R4).addReg(PPC32::R4);
1324 default: assert(0 && "Unknown class!");
1330 /// visitCallInst - Push args on stack and do a procedure call instruction.
1331 void ISel::visitCallInst(CallInst &CI) {
1332 MachineInstr *TheCall;
1333 if (Function *F = CI.getCalledFunction()) {
1334 // Is it an intrinsic function call?
1335 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1336 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1340 // Emit a CALL instruction with PC-relative displacement.
1341 TheCall = BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(F, true);
1342 } else { // Emit an indirect call through the CTR
1343 unsigned Reg = getReg(CI.getCalledValue());
1344 BuildMI(PPC32::MTSPR, 2).addZImm(9).addReg(Reg);
1345 TheCall = BuildMI(PPC32::CALLindirect, 1).addZImm(20).addZImm(0);
1348 std::vector<ValueRecord> Args;
1349 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1350 Args.push_back(ValueRecord(CI.getOperand(i)));
1352 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1353 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1357 /// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
1359 static Value *dyncastIsNan(Value *V) {
1360 if (CallInst *CI = dyn_cast<CallInst>(V))
1361 if (Function *F = CI->getCalledFunction())
1362 if (F->getIntrinsicID() == Intrinsic::isunordered)
1363 return CI->getOperand(1);
1367 /// isOnlyUsedByUnorderedComparisons - Return true if this value is only used by
1368 /// or's whos operands are all calls to the isnan predicate.
1369 static bool isOnlyUsedByUnorderedComparisons(Value *V) {
1370 assert(dyncastIsNan(V) && "The value isn't an isnan call!");
1372 // Check all uses, which will be or's of isnans if this predicate is true.
1373 for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){
1374 Instruction *I = cast<Instruction>(*UI);
1375 if (I->getOpcode() != Instruction::Or) return false;
1376 if (I->getOperand(0) != V && !dyncastIsNan(I->getOperand(0))) return false;
1377 if (I->getOperand(1) != V && !dyncastIsNan(I->getOperand(1))) return false;
1383 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1384 /// function, lowering any calls to unknown intrinsic functions into the
1385 /// equivalent LLVM code.
1387 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1388 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1389 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1390 if (CallInst *CI = dyn_cast<CallInst>(I++))
1391 if (Function *F = CI->getCalledFunction())
1392 switch (F->getIntrinsicID()) {
1393 case Intrinsic::not_intrinsic:
1394 case Intrinsic::vastart:
1395 case Intrinsic::vacopy:
1396 case Intrinsic::vaend:
1397 case Intrinsic::returnaddress:
1398 case Intrinsic::frameaddress:
1399 // FIXME: should lower this ourselves
1400 // case Intrinsic::isunordered:
1401 // We directly implement these intrinsics
1403 case Intrinsic::readio: {
1404 // On PPC, memory operations are in-order. Lower this intrinsic
1405 // into a volatile load.
1406 Instruction *Before = CI->getPrev();
1407 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1408 CI->replaceAllUsesWith(LI);
1409 BB->getInstList().erase(CI);
1412 case Intrinsic::writeio: {
1413 // On PPC, memory operations are in-order. Lower this intrinsic
1414 // into a volatile store.
1415 Instruction *Before = CI->getPrev();
1416 StoreInst *LI = new StoreInst(CI->getOperand(1),
1417 CI->getOperand(2), true, CI);
1418 CI->replaceAllUsesWith(LI);
1419 BB->getInstList().erase(CI);
1423 // All other intrinsic calls we must lower.
1424 Instruction *Before = CI->getPrev();
1425 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1426 if (Before) { // Move iterator to instruction after call
1434 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1435 unsigned TmpReg1, TmpReg2, TmpReg3;
1437 case Intrinsic::vastart:
1438 // Get the address of the first vararg value...
1439 TmpReg1 = getReg(CI);
1440 addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex);
1443 case Intrinsic::vacopy:
1444 TmpReg1 = getReg(CI);
1445 TmpReg2 = getReg(CI.getOperand(1));
1446 BuildMI(BB, PPC32::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
1448 case Intrinsic::vaend: return;
1450 case Intrinsic::returnaddress:
1451 case Intrinsic::frameaddress:
1452 TmpReg1 = getReg(CI);
1453 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1454 if (ID == Intrinsic::returnaddress) {
1455 // Just load the return address
1456 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, TmpReg1),
1457 ReturnAddressIndex);
1459 addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1),
1460 ReturnAddressIndex, -4, false);
1463 // Values other than zero are not implemented yet.
1464 BuildMI(BB, PPC32::ADDI, 2, TmpReg1).addReg(PPC32::R0).addImm(0);
1469 // This may be useful for supporting isunordered
1470 case Intrinsic::isnan:
1471 // If this is only used by 'isunordered' style comparisons, don't emit it.
1472 if (isOnlyUsedByUnorderedComparisons(&CI)) return;
1473 TmpReg1 = getReg(CI.getOperand(1));
1474 emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
1475 TmpReg2 = makeAnotherReg(Type::IntTy);
1476 BuildMI(BB, PPC32::MFCR, TmpReg2);
1477 TmpReg3 = getReg(CI);
1478 BuildMI(BB, PPC32::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
1482 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1486 /// visitSimpleBinary - Implement simple binary operators for integral types...
1487 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1490 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1491 unsigned DestReg = getReg(B);
1492 MachineBasicBlock::iterator MI = BB->end();
1493 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1494 unsigned Class = getClassB(B.getType());
1496 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
1499 /// emitBinaryFPOperation - This method handles emission of floating point
1500 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
1501 void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
1502 MachineBasicBlock::iterator IP,
1503 Value *Op0, Value *Op1,
1504 unsigned OperatorClass, unsigned DestReg) {
1506 // Special case: op Reg, <const fp>
1507 if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1)) {
1508 // Create a constant pool entry for this constant.
1509 MachineConstantPool *CP = F->getConstantPool();
1510 unsigned CPI = CP->getConstantPoolIndex(Op1C);
1511 const Type *Ty = Op1->getType();
1513 static const unsigned OpcodeTab[][4] = {
1514 { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
1515 { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
1518 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1519 unsigned TempReg = makeAnotherReg(Ty);
1520 unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
1521 addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
1523 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1524 unsigned Op0r = getReg(Op0, BB, IP);
1525 BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(TempReg);
1529 // Special case: R1 = op <const fp>, R2
1530 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1531 if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
1533 unsigned op1Reg = getReg(Op1, BB, IP);
1534 BuildMI(*BB, IP, PPC32::FNEG, 1, DestReg).addReg(op1Reg);
1537 // R1 = op CST, R2 --> R1 = opr R2, CST
1539 // Create a constant pool entry for this constant.
1540 MachineConstantPool *CP = F->getConstantPool();
1541 unsigned CPI = CP->getConstantPoolIndex(CFP);
1542 const Type *Ty = CFP->getType();
1544 static const unsigned OpcodeTab[][4] = {
1545 { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
1546 { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
1549 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1550 unsigned TempReg = makeAnotherReg(Ty);
1551 unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
1552 addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
1554 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1555 unsigned Op1r = getReg(Op1, BB, IP);
1556 BuildMI(*BB, IP, Opcode, DestReg).addReg(TempReg).addReg(Op1r);
1561 static const unsigned OpcodeTab[] = {
1562 PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV
1565 unsigned Opcode = OpcodeTab[OperatorClass];
1566 unsigned Op0r = getReg(Op0, BB, IP);
1567 unsigned Op1r = getReg(Op1, BB, IP);
1568 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1571 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1572 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1575 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1576 /// and constant expression support.
1578 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1579 MachineBasicBlock::iterator IP,
1580 Value *Op0, Value *Op1,
1581 unsigned OperatorClass, unsigned DestReg) {
1582 unsigned Class = getClassB(Op0->getType());
1584 // Arithmetic and Bitwise operators
1585 static const unsigned OpcodeTab[] = {
1586 PPC32::ADD, PPC32::SUB, PPC32::AND, PPC32::OR, PPC32::XOR
1588 // Otherwise, code generate the full operation with a constant.
1589 static const unsigned BottomTab[] = {
1590 PPC32::ADDC, PPC32::SUBC, PPC32::AND, PPC32::OR, PPC32::XOR
1592 static const unsigned TopTab[] = {
1593 PPC32::ADDE, PPC32::SUBFE, PPC32::AND, PPC32::OR, PPC32::XOR
1597 assert(OperatorClass < 2 && "No logical ops for FP!");
1598 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
1602 if (Op0->getType() == Type::BoolTy) {
1603 if (OperatorClass == 3)
1604 // If this is an or of two isnan's, emit an FP comparison directly instead
1605 // of or'ing two isnan's together.
1606 if (Value *LHS = dyncastIsNan(Op0))
1607 if (Value *RHS = dyncastIsNan(Op1)) {
1608 unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
1609 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1610 emitUCOM(MBB, IP, Op0Reg, Op1Reg);
1611 BuildMI(*MBB, IP, PPC32::MFCR, TmpReg);
1612 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
1613 .addImm(31).addImm(31);
1618 // sub 0, X -> neg X
1619 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
1620 if (OperatorClass == 1 && CI->isNullValue()) {
1621 unsigned op1Reg = getReg(Op1, MBB, IP);
1622 BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg).addReg(op1Reg);
1624 if (Class == cLong) {
1625 unsigned zeroes = makeAnotherReg(Type::IntTy);
1626 unsigned overflow = makeAnotherReg(Type::IntTy);
1627 unsigned T = makeAnotherReg(Type::IntTy);
1628 BuildMI(*MBB, IP, PPC32::CNTLZW, 1, zeroes).addReg(op1Reg);
1629 BuildMI(*MBB, IP, PPC32::RLWINM, 4, overflow).addReg(zeroes).addImm(27)
1630 .addImm(5).addImm(31);
1631 BuildMI(*MBB, IP, PPC32::ADD, 2, T).addReg(op1Reg+1).addReg(overflow);
1632 BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg+1).addReg(T);
1637 // Special case: op Reg, <const int>
1638 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
1639 unsigned Op0r = getReg(Op0, MBB, IP);
1641 // xor X, -1 -> not X
1642 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1643 BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1644 if (Class == cLong) // Invert the top part too
1645 BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg+1).addReg(Op0r+1)
1650 unsigned Opcode = OpcodeTab[OperatorClass];
1651 unsigned Op1r = getReg(Op1, MBB, IP);
1653 if (Class != cLong) {
1654 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1658 // If the constant is zero in the low 32-bits, just copy the low part
1659 // across and apply the normal 32-bit operation to the high parts. There
1660 // will be no carry or borrow into the top.
1661 if (cast<ConstantInt>(Op1C)->getRawValue() == 0) {
1662 if (OperatorClass != 2) // All but and...
1663 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1665 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1666 BuildMI(*MBB, IP, Opcode, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1670 // If this is a long value and the high or low bits have a special
1671 // property, emit some special cases.
1672 unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
1674 // If this is a logical operation and the top 32-bits are zero, just
1675 // operate on the lower 32.
1676 if (Op1h == 0 && OperatorClass > 1) {
1677 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1678 if (OperatorClass != 2) // All but and
1679 BuildMI(*MBB, IP, PPC32::OR, 2,DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
1681 BuildMI(*MBB, IP, PPC32::ADDI, 2,DestReg+1).addReg(PPC32::R0).addImm(0);
1685 // TODO: We could handle lots of other special cases here, such as AND'ing
1686 // with 0xFFFFFFFF00000000 -> noop, etc.
1688 BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r)
1690 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
1695 unsigned Op0r = getReg(Op0, MBB, IP);
1696 unsigned Op1r = getReg(Op1, MBB, IP);
1698 if (Class != cLong) {
1699 unsigned Opcode = OpcodeTab[OperatorClass];
1700 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1702 BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r)
1704 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
1710 /// doMultiply - Emit appropriate instructions to multiply together the
1711 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1712 /// result should be given as DestTy.
1714 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
1715 unsigned DestReg, const Type *DestTy,
1716 unsigned op0Reg, unsigned op1Reg) {
1717 unsigned Class = getClass(DestTy);
1720 BuildMI(*MBB, MBBI, PPC32::MULHW, 2, DestReg+1).addReg(op0Reg+1)
1725 BuildMI(*MBB, MBBI, PPC32::MULLW, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1728 assert(0 && "doMultiply cannot operate on unknown type!");
1732 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1733 // returns zero when the input is not exactly a power of two.
1734 static unsigned ExactLog2(unsigned Val) {
1735 if (Val == 0 || (Val & (Val-1))) return 0;
1745 /// doMultiplyConst - This function is specialized to efficiently codegen an 8,
1746 /// 16, or 32-bit integer multiply by a constant.
1748 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1749 MachineBasicBlock::iterator IP,
1750 unsigned DestReg, const Type *DestTy,
1751 unsigned op0Reg, unsigned ConstRHS) {
1752 unsigned Class = getClass(DestTy);
1753 // Handle special cases here.
1756 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1759 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(op0Reg).addReg(op0Reg);
1762 BuildMI(*MBB, IP, PPC32::ADD, 2,DestReg).addReg(op0Reg).addReg(op0Reg);
1766 // If the element size is exactly a power of 2, use a shift to get it.
1767 if (unsigned Shift = ExactLog2(ConstRHS)) {
1769 default: assert(0 && "Unknown class for this function!");
1773 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(op0Reg)
1774 .addImm(Shift-1).addImm(0).addImm(31-Shift-1);
1779 // Most general case, emit a normal multiply...
1780 unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
1781 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1782 BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg1).addReg(PPC32::R0)
1783 .addImm(ConstRHS >> 16);
1784 BuildMI(*MBB, IP, PPC32::ORI, 2, TmpReg2).addReg(TmpReg1).addImm(ConstRHS);
1786 // Emit a MUL to multiply the register holding the index by
1787 // elementSize, putting the result in OffsetReg.
1788 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg2);
1791 void ISel::visitMul(BinaryOperator &I) {
1792 unsigned ResultReg = getReg(I);
1794 Value *Op0 = I.getOperand(0);
1795 Value *Op1 = I.getOperand(1);
1797 MachineBasicBlock::iterator IP = BB->end();
1798 emitMultiply(BB, IP, Op0, Op1, ResultReg);
1801 void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
1802 Value *Op0, Value *Op1, unsigned DestReg) {
1803 MachineBasicBlock &BB = *MBB;
1804 TypeClass Class = getClass(Op0->getType());
1806 // Simple scalar multiply?
1807 unsigned Op0Reg = getReg(Op0, &BB, IP);
1812 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1813 unsigned Val = (unsigned)CI->getRawValue(); // Isn't a 64-bit constant
1814 doMultiplyConst(&BB, IP, DestReg, Op0->getType(), Op0Reg, Val);
1816 unsigned Op1Reg = getReg(Op1, &BB, IP);
1817 doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
1821 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
1827 // Long value. We have to do things the hard way...
1828 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1829 unsigned CLow = CI->getRawValue();
1830 unsigned CHi = CI->getRawValue() >> 32;
1833 // If the low part of the constant is all zeros, things are simple.
1834 BuildMI(BB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1835 doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
1839 // Multiply the two low parts
1840 unsigned OverflowReg = 0;
1842 BuildMI(BB, IP, PPC32::OR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
1844 unsigned TmpRegL = makeAnotherReg(Type::UIntTy);
1845 unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
1846 OverflowReg = makeAnotherReg(Type::UIntTy);
1847 BuildMI(BB, IP, PPC32::ADDIS, 2, TmpRegL).addReg(PPC32::R0)
1848 .addImm(CLow >> 16);
1849 BuildMI(BB, IP, PPC32::ORI, 2, Op1RegL).addReg(TmpRegL).addImm(CLow);
1850 BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1RegL);
1851 BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg)
1855 unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
1856 doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
1858 unsigned AHBLplusOverflowReg;
1860 AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1861 BuildMI(BB, IP, PPC32::ADD, 2,
1862 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1864 AHBLplusOverflowReg = AHBLReg;
1868 BuildMI(BB, IP, PPC32::OR, 2, DestReg+1).addReg(AHBLplusOverflowReg)
1869 .addReg(AHBLplusOverflowReg);
1871 unsigned ALBHReg = makeAnotherReg(Type::UIntTy);
1872 doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
1874 BuildMI(BB, IP, PPC32::ADD, 2,
1875 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1880 // General 64x64 multiply
1882 unsigned Op1Reg = getReg(Op1, &BB, IP);
1884 // Multiply the two low parts...
1885 BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
1887 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1888 BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg);
1890 unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
1891 BuildMI(BB, IP, PPC32::MULLW, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1893 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1894 BuildMI(BB, IP, PPC32::ADD, 2, AHBLplusOverflowReg).addReg(AHBLReg)
1895 .addReg(OverflowReg);
1897 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1898 BuildMI(BB, IP, PPC32::MULLW, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1900 BuildMI(BB, IP, PPC32::ADD, 2,
1901 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1905 /// visitDivRem - Handle division and remainder instructions... these
1906 /// instruction both require the same instructions to be generated, they just
1907 /// select the result from a different register. Note that both of these
1908 /// instructions work differently for signed and unsigned operands.
1910 void ISel::visitDivRem(BinaryOperator &I) {
1911 unsigned ResultReg = getReg(I);
1912 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
1914 MachineBasicBlock::iterator IP = BB->end();
1915 emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div,
1919 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1920 MachineBasicBlock::iterator IP,
1921 Value *Op0, Value *Op1, bool isDiv,
1922 unsigned ResultReg) {
1923 const Type *Ty = Op0->getType();
1924 unsigned Class = getClass(Ty);
1926 case cFP: // Floating point divide
1928 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
1930 } else { // Floating point remainder...
1931 unsigned Op0Reg = getReg(Op0, BB, IP);
1932 unsigned Op1Reg = getReg(Op1, BB, IP);
1933 MachineInstr *TheCall =
1934 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("fmod", true);
1935 std::vector<ValueRecord> Args;
1936 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1937 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1938 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1942 static const char *FnName[] =
1943 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1944 unsigned Op0Reg = getReg(Op0, BB, IP);
1945 unsigned Op1Reg = getReg(Op1, BB, IP);
1946 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1947 MachineInstr *TheCall =
1948 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol(FnName[NameIdx], true);
1950 std::vector<ValueRecord> Args;
1951 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1952 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1953 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1956 case cByte: case cShort: case cInt:
1957 break; // Small integrals, handled below...
1958 default: assert(0 && "Unknown class!");
1961 // Special case signed division by power of 2.
1963 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
1964 assert(Class != cLong && "This doesn't handle 64-bit divides!");
1965 int V = CI->getValue();
1967 if (V == 1) { // X /s 1 => X
1968 unsigned Op0Reg = getReg(Op0, BB, IP);
1969 BuildMI(*BB, IP, PPC32::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
1973 if (V == -1) { // X /s -1 => -X
1974 unsigned Op0Reg = getReg(Op0, BB, IP);
1975 BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(Op0Reg);
1980 if (V < 0) { // Not a positive power of 2?
1982 isNeg = true; // Maybe it's a negative power of 2.
1984 if (unsigned Log = ExactLog2(V)) {
1986 unsigned Op0Reg = getReg(Op0, BB, IP);
1987 unsigned TmpReg = makeAnotherReg(Op0->getType());
1989 BuildMI(*BB, IP, PPC32::SRAWI,2, TmpReg).addReg(Op0Reg).addImm(Log-1);
1991 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(Op0Reg).addReg(Op0Reg);
1993 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
1994 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg2).addReg(TmpReg).addImm(Log)
1995 .addImm(32-Log).addImm(31);
1997 unsigned TmpReg3 = makeAnotherReg(Op0->getType());
1998 BuildMI(*BB, IP, PPC32::ADD, 2, TmpReg3).addReg(Op0Reg).addReg(TmpReg2);
2000 unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
2001 BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg4).addReg(Op0Reg).addImm(Log);
2004 BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(TmpReg4);
2009 unsigned Op0Reg = getReg(Op0, BB, IP);
2010 unsigned Op1Reg = getReg(Op1, BB, IP);
2013 if (Ty->isSigned()) {
2014 BuildMI(*BB, IP, PPC32::DIVW, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2016 BuildMI(*BB, IP,PPC32::DIVWU, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2018 } else { // Remainder
2019 unsigned TmpReg1 = makeAnotherReg(Op0->getType());
2020 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2022 if (Ty->isSigned()) {
2023 BuildMI(*BB, IP, PPC32::DIVW, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
2025 BuildMI(*BB, IP, PPC32::DIVWU, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
2027 BuildMI(*BB, IP, PPC32::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
2028 BuildMI(*BB, IP, PPC32::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
2033 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2034 /// for constant immediate shift values, and for constant immediate
2035 /// shift values equal to 1. Even the general case is sort of special,
2036 /// because the shift amount has to be in CL, not just any old register.
2038 void ISel::visitShiftInst(ShiftInst &I) {
2039 MachineBasicBlock::iterator IP = BB->end ();
2040 emitShiftOperation(BB, IP, I.getOperand (0), I.getOperand (1),
2041 I.getOpcode () == Instruction::Shl, I.getType (),
2045 /// emitShiftOperation - Common code shared between visitShiftInst and
2046 /// constant expression support.
2048 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
2049 MachineBasicBlock::iterator IP,
2050 Value *Op, Value *ShiftAmount, bool isLeftShift,
2051 const Type *ResultTy, unsigned DestReg) {
2052 unsigned SrcReg = getReg (Op, MBB, IP);
2053 bool isSigned = ResultTy->isSigned ();
2054 unsigned Class = getClass (ResultTy);
2056 // Longs, as usual, are handled specially...
2057 if (Class == cLong) {
2058 // If we have a constant shift, we can generate much more efficient code
2059 // than otherwise...
2061 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2062 unsigned Amount = CUI->getValue();
2065 // FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA
2066 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
2067 .addImm(Amount).addImm(0).addImm(31-Amount);
2068 BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg)
2069 .addImm(Amount).addImm(32-Amount).addImm(31);
2070 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2071 .addImm(Amount).addImm(0).addImm(31-Amount);
2073 // FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA
2074 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2075 .addImm(32-Amount).addImm(Amount).addImm(31);
2076 BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1)
2077 .addImm(32-Amount).addImm(0).addImm(Amount-1);
2078 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
2079 .addImm(32-Amount).addImm(Amount).addImm(31);
2081 } else { // Shifting more than 32 bits
2085 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg)
2086 .addImm(Amount).addImm(0).addImm(31-Amount);
2088 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg)
2091 BuildMI(*MBB, IP, PPC32::ADDI, 2,DestReg).addReg(PPC32::R0).addImm(0);
2095 BuildMI(*MBB, IP, PPC32::SRAWI, 2, DestReg).addReg(SrcReg+1)
2098 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg+1)
2099 .addImm(32-Amount).addImm(Amount).addImm(31);
2101 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg+1)
2104 BuildMI(*MBB, IP,PPC32::ADDI,2,DestReg+1).addReg(PPC32::R0).addImm(0);
2108 unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
2109 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
2110 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
2111 unsigned TmpReg4 = makeAnotherReg(Type::IntTy);
2112 unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
2113 unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
2114 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2117 BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
2119 BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg2).addReg(SrcReg+1)
2120 .addReg(ShiftAmountReg);
2121 BuildMI(*MBB, IP, PPC32::SRW, 2,TmpReg3).addReg(SrcReg).addReg(TmpReg1);
2122 BuildMI(*MBB, IP, PPC32::OR, 2,TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
2123 BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
2125 BuildMI(*MBB, IP, PPC32::SLW, 2,TmpReg6).addReg(SrcReg).addReg(TmpReg5);
2126 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TmpReg4)
2128 BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg)
2129 .addReg(ShiftAmountReg);
2132 // FIXME: Unimplemented
2133 // Page C-3 of the PowerPC 32bit Programming Environments Manual
2134 std::cerr << "Unimplemented: signed right shift\n";
2137 BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
2139 BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg2).addReg(SrcReg)
2140 .addReg(ShiftAmountReg);
2141 BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg3).addReg(SrcReg+1)
2143 BuildMI(*MBB, IP, PPC32::OR, 2, TmpReg4).addReg(TmpReg2)
2145 BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
2147 BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg6).addReg(SrcReg+1)
2149 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TmpReg4)
2151 BuildMI(*MBB, IP, PPC32::SRW, 2, DestReg+1).addReg(SrcReg+1)
2152 .addReg(ShiftAmountReg);
2159 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2160 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2161 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2162 unsigned Amount = CUI->getValue();
2165 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2166 .addImm(Amount).addImm(0).addImm(31-Amount);
2169 BuildMI(*MBB, IP, PPC32::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
2171 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2172 .addImm(32-Amount).addImm(Amount).addImm(31);
2175 } else { // The shift amount is non-constant.
2176 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2179 BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg)
2180 .addReg(ShiftAmountReg);
2182 BuildMI(*MBB, IP, isSigned ? PPC32::SRAW : PPC32::SRW, 2, DestReg)
2183 .addReg(SrcReg).addReg(ShiftAmountReg);
2189 /// visitLoadInst - Implement LLVM load instructions
2191 void ISel::visitLoadInst(LoadInst &I) {
2192 static const unsigned Opcodes[] = {
2193 PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS
2195 unsigned Class = getClassB(I.getType());
2196 unsigned Opcode = Opcodes[Class];
2197 if (I.getType() == Type::DoubleTy) Opcode = PPC32::LFD;
2199 unsigned DestReg = getReg(I);
2201 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
2202 unsigned FI = getFixedSizedAllocaFI(AI);
2203 if (Class == cLong) {
2204 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg), FI);
2205 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg+1), FI, 4);
2207 addFrameReference(BuildMI(BB, Opcode, 2, DestReg), FI);
2210 unsigned SrcAddrReg = getReg(I.getOperand(0));
2212 if (Class == cLong) {
2213 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(SrcAddrReg);
2214 BuildMI(BB, PPC32::LWZ, 2, DestReg+1).addImm(4).addReg(SrcAddrReg);
2216 BuildMI(BB, Opcode, 2, DestReg).addImm(0).addReg(SrcAddrReg);
2221 /// visitStoreInst - Implement LLVM store instructions
2223 void ISel::visitStoreInst(StoreInst &I) {
2224 unsigned ValReg = getReg(I.getOperand(0));
2225 unsigned AddressReg = getReg(I.getOperand(1));
2227 const Type *ValTy = I.getOperand(0)->getType();
2228 unsigned Class = getClassB(ValTy);
2230 if (Class == cLong) {
2231 BuildMI(BB, PPC32::STW, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
2232 BuildMI(BB, PPC32::STW, 3).addReg(ValReg+1).addImm(4).addReg(AddressReg);
2236 static const unsigned Opcodes[] = {
2237 PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS
2239 unsigned Opcode = Opcodes[Class];
2240 if (ValTy == Type::DoubleTy) Opcode = PPC32::STFD;
2241 BuildMI(BB, Opcode, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
2245 /// visitCastInst - Here we have various kinds of copying with or without sign
2246 /// extension going on.
2248 void ISel::visitCastInst(CastInst &CI) {
2249 Value *Op = CI.getOperand(0);
2251 unsigned SrcClass = getClassB(Op->getType());
2252 unsigned DestClass = getClassB(CI.getType());
2253 // Noop casts are not emitted: getReg will return the source operand as the
2254 // register to use for any uses of the noop cast.
2255 if (DestClass == SrcClass)
2258 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2259 // of the case are GEP instructions, then the cast does not need to be
2260 // generated explicitly, it will be folded into the GEP.
2261 if (DestClass == cLong && SrcClass == cInt) {
2262 bool AllUsesAreGEPs = true;
2263 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2264 if (!isa<GetElementPtrInst>(*I)) {
2265 AllUsesAreGEPs = false;
2269 // No need to codegen this cast if all users are getelementptr instrs...
2270 if (AllUsesAreGEPs) return;
2273 unsigned DestReg = getReg(CI);
2274 MachineBasicBlock::iterator MI = BB->end();
2275 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2278 /// emitCastOperation - Common code shared between visitCastInst and constant
2279 /// expression cast support.
2281 void ISel::emitCastOperation(MachineBasicBlock *BB,
2282 MachineBasicBlock::iterator IP,
2283 Value *Src, const Type *DestTy,
2285 const Type *SrcTy = Src->getType();
2286 unsigned SrcClass = getClassB(SrcTy);
2287 unsigned DestClass = getClassB(DestTy);
2288 unsigned SrcReg = getReg(Src, BB, IP);
2290 // Implement casts to bool by using compare on the operand followed by set if
2291 // not zero on the result.
2292 if (DestTy == Type::BoolTy) {
2297 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2298 BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg).addImm(-1);
2299 BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
2303 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2304 unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
2305 BuildMI(*BB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
2306 BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1);
2307 BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg2);
2326 // Implement casts between values of the same type class (as determined by
2327 // getClass) by using a register-to-register move.
2328 if (SrcClass == DestClass) {
2329 if (SrcClass <= cInt) {
2330 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2331 } else if (SrcClass == cFP && SrcTy == DestTy) {
2332 BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
2333 } else if (SrcClass == cFP) {
2334 if (SrcTy == Type::FloatTy) { // float -> double
2335 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
2336 BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
2337 } else { // double -> float
2338 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
2339 "Unknown cFP member!");
2340 BuildMI(*BB, IP, PPC32::FRSP, 1, DestReg).addReg(SrcReg);
2342 } else if (SrcClass == cLong) {
2343 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2344 BuildMI(*BB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg+1)
2347 assert(0 && "Cannot handle this type of cast instruction!");
2353 // Handle cast of SMALLER int to LARGER int using a move with sign extension
2354 // or zero extension, depending on whether the source type was signed.
2355 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
2356 SrcClass < DestClass) {
2357 bool isLong = DestClass == cLong;
2358 if (isLong) DestClass = cInt;
2360 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
2361 if (SrcClass < cInt) {
2363 unsigned shift = (SrcClass == cByte) ? 24 : 16;
2364 BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0)
2365 .addImm(shift).addImm(31);
2367 BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH,
2368 1, DestReg).addReg(SrcReg);
2371 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2374 if (isLong) { // Handle upper 32 bits as appropriate...
2375 if (isUnsigned) // Zero out top bits...
2376 BuildMI(*BB, IP, PPC32::ADDI, 2, DestReg+1).addReg(PPC32::R0).addImm(0);
2377 else // Sign extend bottom half...
2378 BuildMI(*BB, IP, PPC32::SRAWI, 2, DestReg+1).addReg(DestReg).addImm(31);
2383 // Special case long -> int ...
2384 if (SrcClass == cLong && DestClass == cInt) {
2385 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2389 // Handle cast of LARGER int to SMALLER int with a clear or sign extend
2390 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
2391 && SrcClass > DestClass) {
2392 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
2394 unsigned shift = (SrcClass == cByte) ? 24 : 16;
2395 BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0)
2396 .addImm(shift).addImm(31);
2398 BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH, 1,
2399 DestReg).addReg(SrcReg);
2404 // Handle casts from integer to floating point now...
2405 if (DestClass == cFP) {
2407 // Emit a library call for long to float conversion
2408 if (SrcClass == cLong) {
2409 std::vector<ValueRecord> Args;
2410 Args.push_back(ValueRecord(SrcReg, SrcTy));
2411 MachineInstr *TheCall =
2412 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("__floatdidf", true);
2413 doCall(ValueRecord(DestReg, DestTy), TheCall, Args);
2417 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2418 switch (SrcTy->getTypeID()) {
2419 case Type::BoolTyID:
2420 case Type::SByteTyID:
2421 BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
2423 case Type::UByteTyID:
2424 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0)
2425 .addImm(24).addImm(31);
2427 case Type::ShortTyID:
2428 BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
2430 case Type::UShortTyID:
2431 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0)
2432 .addImm(16).addImm(31);
2435 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
2437 case Type::UIntTyID:
2438 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
2440 default: // No promotion needed...
2446 // Spill the integer to memory and reload it from there.
2447 // Also spill room for a special conversion constant
2448 int ConstantFrameIndex =
2449 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2451 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2453 unsigned constantHi = makeAnotherReg(Type::IntTy);
2454 unsigned constantLo = makeAnotherReg(Type::IntTy);
2455 unsigned ConstF = makeAnotherReg(Type::DoubleTy);
2456 unsigned TempF = makeAnotherReg(Type::DoubleTy);
2458 if (!SrcTy->isSigned()) {
2459 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0)
2461 BuildMI(*BB, IP, PPC32::ADDI, 2, constantLo).addReg(PPC32::R0).addImm(0);
2462 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2463 ConstantFrameIndex);
2464 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo),
2465 ConstantFrameIndex, 4);
2466 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2468 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(SrcReg),
2470 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF),
2471 ConstantFrameIndex);
2472 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
2473 BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
2475 unsigned TempLo = makeAnotherReg(Type::IntTy);
2476 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0)
2478 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantLo).addReg(PPC32::R0)
2480 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2481 ConstantFrameIndex);
2482 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo),
2483 ConstantFrameIndex, 4);
2484 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2486 BuildMI(*BB, IP, PPC32::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
2487 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(TempLo),
2489 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF),
2490 ConstantFrameIndex);
2491 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
2492 BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF ).addReg(ConstF);
2497 // Handle casts from floating point to integer now...
2498 if (SrcClass == cFP) {
2500 // emit library call
2501 if (DestClass == cLong) {
2502 std::vector<ValueRecord> Args;
2503 Args.push_back(ValueRecord(SrcReg, SrcTy));
2504 MachineInstr *TheCall =
2505 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("__fixdfdi", true);
2506 doCall(ValueRecord(DestReg, DestTy), TheCall, Args);
2511 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2513 // load into 32 bit value, and then truncate as necessary
2514 // FIXME: This is wrong for unsigned dest types
2515 //if (DestTy->isSigned()) {
2516 unsigned TempReg = makeAnotherReg(Type::DoubleTy);
2517 BuildMI(*BB, IP, PPC32::FCTIWZ, 1, TempReg).addReg(SrcReg);
2518 addFrameReference(BuildMI(*BB, IP, PPC32::STFD, 3)
2519 .addReg(TempReg), ValueFrameIdx);
2520 addFrameReference(BuildMI(*BB, IP, PPC32::LWZ, 2, DestReg),
2525 // FIXME: Truncate return value
2529 // Anything we haven't handled already, we can't (yet) handle at all.
2530 assert(0 && "Unhandled cast instruction!");
2534 /// visitVANextInst - Implement the va_next instruction...
2536 void ISel::visitVANextInst(VANextInst &I) {
2537 unsigned VAList = getReg(I.getOperand(0));
2538 unsigned DestReg = getReg(I);
2541 switch (I.getArgType()->getTypeID()) {
2544 assert(0 && "Error: bad type for va_next instruction!");
2546 case Type::PointerTyID:
2547 case Type::UIntTyID:
2551 case Type::ULongTyID:
2552 case Type::LongTyID:
2553 case Type::DoubleTyID:
2558 // Increment the VAList pointer...
2559 BuildMI(BB, PPC32::ADDI, 2, DestReg).addReg(VAList).addImm(Size);
2562 void ISel::visitVAArgInst(VAArgInst &I) {
2563 unsigned VAList = getReg(I.getOperand(0));
2564 unsigned DestReg = getReg(I);
2566 switch (I.getType()->getTypeID()) {
2569 assert(0 && "Error: bad type for va_next instruction!");
2571 case Type::PointerTyID:
2572 case Type::UIntTyID:
2574 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(VAList);
2576 case Type::ULongTyID:
2577 case Type::LongTyID:
2578 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(VAList);
2579 BuildMI(BB, PPC32::LWZ, 2, DestReg+1).addImm(4).addReg(VAList);
2581 case Type::DoubleTyID:
2582 BuildMI(BB, PPC32::LFD, 2, DestReg).addImm(0).addReg(VAList);
2587 /// visitGetElementPtrInst - instruction-select GEP instructions
2589 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2590 unsigned outputReg = getReg(I);
2591 emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(),
2595 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2596 MachineBasicBlock::iterator IP,
2597 Value *Src, User::op_iterator IdxBegin,
2598 User::op_iterator IdxEnd, unsigned TargetReg) {
2599 const TargetData &TD = TM.getTargetData();
2600 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
2601 Src = CPR->getValue();
2603 std::vector<Value*> GEPOps;
2604 GEPOps.resize(IdxEnd-IdxBegin+1);
2606 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2608 std::vector<const Type*> GEPTypes;
2609 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2610 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2612 // Keep emitting instructions until we consume the entire GEP instruction.
2613 while (!GEPOps.empty()) {
2614 if (GEPTypes.empty()) {
2615 // Load the base pointer into a register.
2616 unsigned Reg = getReg(Src, MBB, IP);
2617 BuildMI(*MBB, IP, PPC32::OR, 2, TargetReg).addReg(Reg).addReg(Reg);
2618 break; // we are now done
2620 // It's an array or pointer access: [ArraySize x ElementType].
2621 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2622 Value *idx = GEPOps.back();
2623 GEPOps.pop_back(); // Consume a GEP operand
2624 GEPTypes.pop_back();
2626 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
2627 // operand. Handle this case directly now...
2628 if (CastInst *CI = dyn_cast<CastInst>(idx))
2629 if (CI->getOperand(0)->getType() == Type::IntTy ||
2630 CI->getOperand(0)->getType() == Type::UIntTy)
2631 idx = CI->getOperand(0);
2633 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2634 // must find the size of the pointed-to type (Not coincidentally, the next
2635 // type is the type of the elements in the array).
2636 const Type *ElTy = SqTy->getElementType();
2637 unsigned elementSize = TD.getTypeSize(ElTy);
2639 if (idx == Constant::getNullValue(idx->getType())) {
2640 // GEP with idx 0 is a no-op
2641 } else if (elementSize == 1) {
2642 // If the element size is 1, we don't have to multiply, just add
2643 unsigned idxReg = getReg(idx, MBB, IP);
2644 unsigned Reg = makeAnotherReg(Type::UIntTy);
2645 BuildMI(*MBB, IP, PPC32::ADD, 2,TargetReg).addReg(Reg).addReg(idxReg);
2646 --IP; // Insert the next instruction before this one.
2647 TargetReg = Reg; // Codegen the rest of the GEP into this
2649 unsigned idxReg = getReg(idx, MBB, IP);
2650 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2652 // Make sure we can back the iterator up to point to the first
2653 // instruction emitted.
2654 MachineBasicBlock::iterator BeforeIt = IP;
2655 if (IP == MBB->begin())
2656 BeforeIt = MBB->end();
2659 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2661 // Emit an ADD to add OffsetReg to the basePtr.
2662 unsigned Reg = makeAnotherReg(Type::UIntTy);
2663 BuildMI(*MBB, IP, PPC32::ADD, 2, TargetReg).addReg(Reg).addReg(OffsetReg);
2665 // Step to the first instruction of the multiply.
2666 if (BeforeIt == MBB->end())
2671 TargetReg = Reg; // Codegen the rest of the GEP into this
2676 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2677 /// frame manager, otherwise do it the hard way.
2679 void ISel::visitAllocaInst(AllocaInst &I) {
2680 // If this is a fixed size alloca in the entry block for the function, we
2681 // statically stack allocate the space, so we don't need to do anything here.
2683 if (dyn_castFixedAlloca(&I)) return;
2685 // Find the data size of the alloca inst's getAllocatedType.
2686 const Type *Ty = I.getAllocatedType();
2687 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2689 // Create a register to hold the temporary result of multiplying the type size
2690 // constant by the variable amount.
2691 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2692 unsigned SrcReg1 = getReg(I.getArraySize());
2694 // TotalSizeReg = mul <numelements>, <TypeSize>
2695 MachineBasicBlock::iterator MBBI = BB->end();
2696 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2698 // AddedSize = add <TotalSizeReg>, 15
2699 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2700 BuildMI(BB, PPC32::ADD, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
2702 // AlignedSize = and <AddedSize>, ~15
2703 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2704 BuildMI(BB, PPC32::RLWNM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
2705 .addImm(0).addImm(27);
2707 // Subtract size from stack pointer, thereby allocating some space.
2708 BuildMI(BB, PPC32::SUB, 2, PPC32::R1).addReg(PPC32::R1).addReg(AlignedSize);
2710 // Put a pointer to the space into the result register, by copying
2711 // the stack pointer.
2712 BuildMI(BB, PPC32::OR, 2, getReg(I)).addReg(PPC32::R1).addReg(PPC32::R1);
2714 // Inform the Frame Information that we have just allocated a variable-sized
2716 F->getFrameInfo()->CreateVariableSizedObject();
2719 /// visitMallocInst - Malloc instructions are code generated into direct calls
2720 /// to the library malloc.
2722 void ISel::visitMallocInst(MallocInst &I) {
2723 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2726 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2727 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2729 Arg = makeAnotherReg(Type::UIntTy);
2730 unsigned Op0Reg = getReg(I.getOperand(0));
2731 MachineBasicBlock::iterator MBBI = BB->end();
2732 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2735 std::vector<ValueRecord> Args;
2736 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2737 MachineInstr *TheCall =
2738 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("malloc", true);
2739 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2743 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2746 void ISel::visitFreeInst(FreeInst &I) {
2747 std::vector<ValueRecord> Args;
2748 Args.push_back(ValueRecord(I.getOperand(0)));
2749 MachineInstr *TheCall =
2750 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("free", true);
2751 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2754 /// createPPC32SimpleInstructionSelector - This pass converts an LLVM function
2755 /// into a machine code representation is a very simple peep-hole fashion. The
2756 /// generated code sucks but the implementation is nice and simple.
2758 FunctionPass *llvm::createPPCSimpleInstructionSelector(TargetMachine &TM) {
2759 return new ISel(TM);