1 //===-- InstSelectSimple.cpp - A simple instruction selector for PowerPC --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "isel"
12 #include "PowerPCInstrBuilder.h"
13 #include "PowerPCInstrInfo.h"
14 #include "llvm/Constants.h"
15 #include "llvm/DerivedTypes.h"
16 #include "llvm/Function.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/CodeGen/IntrinsicLowering.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/MRegisterInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/GetElementPtrTypeIterator.h"
27 #include "llvm/Support/InstVisitor.h"
28 #include "Support/Debug.h"
33 /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
34 /// PPC Representation.
37 cByte, cShort, cInt, cFP, cLong
41 /// getClass - Turn a primitive type into a "class" number which is based on the
42 /// size of the type, and whether or not it is floating point.
44 static inline TypeClass getClass(const Type *Ty) {
45 switch (Ty->getTypeID()) {
47 case Type::UByteTyID: return cByte; // Byte operands are class #0
49 case Type::UShortTyID: return cShort; // Short operands are class #1
52 case Type::PointerTyID: return cInt; // Ints and pointers are class #2
55 case Type::DoubleTyID: return cFP; // Floating Point is #3
58 case Type::ULongTyID: return cLong; // Longs are class #4
60 assert(0 && "Invalid type to getClass!");
61 return cByte; // not reached
65 // getClassB - Just like getClass, but treat boolean values as ints.
66 static inline TypeClass getClassB(const Type *Ty) {
67 if (Ty == Type::BoolTy) return cInt;
72 struct ISel : public FunctionPass, InstVisitor<ISel> {
74 MachineFunction *F; // The function we are compiling into
75 MachineBasicBlock *BB; // The current MBB we are compiling
76 int VarArgsFrameIndex; // FrameIndex for start of varargs area
77 int ReturnAddressIndex; // FrameIndex for the return address
79 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
81 // External functions used in the Module
82 std::map<std::string, Function*> Func;
84 // MBBMap - Mapping between LLVM BB -> Machine BB
85 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
87 // AllocaMap - Mapping from fixed sized alloca instructions to the
88 // FrameIndex for the alloca.
89 std::map<AllocaInst*, unsigned> AllocaMap;
91 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
93 bool doInitialization(Module &M) {
94 // Add external functions that we may call
95 Type *d = Type::DoubleTy;
96 Type *l = Type::LongTy;
97 Type *ul = Type::ULongTy;
98 // double fmod(double, double);
99 Func["fmod"] = M.getOrInsertFunction("fmod", d, d, d, 0);
100 // long __moddi3(long, long);
101 Func["__moddi3"] = M.getOrInsertFunction("__moddi3", l, l, l, 0);
102 // long __divdi3(long, long);
103 Func["__divdi3"] = M.getOrInsertFunction("__divdi3", l, l, l, 0);
104 // unsigned long __umoddi3(unsigned long, unsigned long);
105 Func["__umoddi3"] = M.getOrInsertFunction("__umoddi3", ul, ul, ul, 0);
106 // unsigned long __udivdi3(unsigned long, unsigned long);
107 Func["__udivdi3"] = M.getOrInsertFunction("__udivdi3", ul, ul, ul, 0);
111 /// runOnFunction - Top level implementation of instruction selection for
112 /// the entire function.
114 bool runOnFunction(Function &Fn) {
115 // First pass over the function, lower any unknown intrinsic functions
116 // with the IntrinsicLowering class.
117 LowerUnknownIntrinsicFunctionCalls(Fn);
119 F = &MachineFunction::construct(&Fn, TM);
121 // Create all of the machine basic blocks for the function...
122 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
123 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
127 // Set up a frame object for the return address. This is used by the
128 // llvm.returnaddress & llvm.frameaddress intrinisics.
129 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
131 // Copy incoming arguments off of the stack...
132 LoadArgumentsToVirtualRegs(Fn);
134 // Instruction select everything except PHI nodes
137 // Select the PHI nodes
144 // We always build a machine code representation for the function
148 virtual const char *getPassName() const {
149 return "PowerPC Simple Instruction Selection";
152 /// visitBasicBlock - This method is called when we are visiting a new basic
153 /// block. This simply creates a new MachineBasicBlock to emit code into
154 /// and adds it to the current MachineFunction. Subsequent visit* for
155 /// instructions will be invoked for all instructions in the basic block.
157 void visitBasicBlock(BasicBlock &LLVM_BB) {
158 BB = MBBMap[&LLVM_BB];
161 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
162 /// function, lowering any calls to unknown intrinsic functions into the
163 /// equivalent LLVM code.
165 void LowerUnknownIntrinsicFunctionCalls(Function &F);
167 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
168 /// from the stack into virtual registers.
170 void LoadArgumentsToVirtualRegs(Function &F);
172 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
173 /// because we have to generate our sources into the source basic blocks,
174 /// not the current one.
176 void SelectPHINodes();
178 // Visitation methods for various instructions. These methods simply emit
179 // fixed PowerPC code for each instruction.
181 // Control flow operators
182 void visitReturnInst(ReturnInst &RI);
183 void visitBranchInst(BranchInst &BI);
189 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
190 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
192 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
193 const std::vector<ValueRecord> &Args, bool isVarArg);
194 void visitCallInst(CallInst &I);
195 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
197 // Arithmetic operators
198 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
199 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
200 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
201 void visitMul(BinaryOperator &B);
203 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
204 void visitRem(BinaryOperator &B) { visitDivRem(B); }
205 void visitDivRem(BinaryOperator &B);
208 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
209 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
210 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
212 // Comparison operators...
213 void visitSetCondInst(SetCondInst &I);
214 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
215 MachineBasicBlock *MBB,
216 MachineBasicBlock::iterator MBBI);
217 void visitSelectInst(SelectInst &SI);
220 // Memory Instructions
221 void visitLoadInst(LoadInst &I);
222 void visitStoreInst(StoreInst &I);
223 void visitGetElementPtrInst(GetElementPtrInst &I);
224 void visitAllocaInst(AllocaInst &I);
225 void visitMallocInst(MallocInst &I);
226 void visitFreeInst(FreeInst &I);
229 void visitShiftInst(ShiftInst &I);
230 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
231 void visitCastInst(CastInst &I);
232 void visitVANextInst(VANextInst &I);
233 void visitVAArgInst(VAArgInst &I);
235 void visitInstruction(Instruction &I) {
236 std::cerr << "Cannot instruction select: " << I;
240 /// promote32 - Make a value 32-bits wide, and put it somewhere.
242 void promote32(unsigned targetReg, const ValueRecord &VR);
244 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
245 /// constant expression GEP support.
247 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
248 Value *Src, User::op_iterator IdxBegin,
249 User::op_iterator IdxEnd, unsigned TargetReg);
251 /// emitCastOperation - Common code shared between visitCastInst and
252 /// constant expression cast support.
254 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
255 Value *Src, const Type *DestTy, unsigned TargetReg);
257 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
258 /// and constant expression support.
260 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
261 MachineBasicBlock::iterator IP,
262 Value *Op0, Value *Op1,
263 unsigned OperatorClass, unsigned TargetReg);
265 /// emitBinaryFPOperation - This method handles emission of floating point
266 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
267 void emitBinaryFPOperation(MachineBasicBlock *BB,
268 MachineBasicBlock::iterator IP,
269 Value *Op0, Value *Op1,
270 unsigned OperatorClass, unsigned TargetReg);
272 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
273 Value *Op0, Value *Op1, unsigned TargetReg);
275 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
276 unsigned DestReg, const Type *DestTy,
277 unsigned Op0Reg, unsigned Op1Reg);
278 void doMultiplyConst(MachineBasicBlock *MBB,
279 MachineBasicBlock::iterator MBBI,
280 unsigned DestReg, const Type *DestTy,
281 unsigned Op0Reg, unsigned Op1Val);
283 void emitDivRemOperation(MachineBasicBlock *BB,
284 MachineBasicBlock::iterator IP,
285 Value *Op0, Value *Op1, bool isDiv,
288 /// emitSetCCOperation - Common code shared between visitSetCondInst and
289 /// constant expression support.
291 void emitSetCCOperation(MachineBasicBlock *BB,
292 MachineBasicBlock::iterator IP,
293 Value *Op0, Value *Op1, unsigned Opcode,
296 /// emitShiftOperation - Common code shared between visitShiftInst and
297 /// constant expression support.
299 void emitShiftOperation(MachineBasicBlock *MBB,
300 MachineBasicBlock::iterator IP,
301 Value *Op, Value *ShiftAmount, bool isLeftShift,
302 const Type *ResultTy, unsigned DestReg);
304 /// emitSelectOperation - Common code shared between visitSelectInst and the
305 /// constant expression support.
306 void emitSelectOperation(MachineBasicBlock *MBB,
307 MachineBasicBlock::iterator IP,
308 Value *Cond, Value *TrueVal, Value *FalseVal,
311 /// copyConstantToRegister - Output the instructions required to put the
312 /// specified constant into the specified register.
314 void copyConstantToRegister(MachineBasicBlock *MBB,
315 MachineBasicBlock::iterator MBBI,
316 Constant *C, unsigned Reg);
318 void emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
319 unsigned LHS, unsigned RHS);
321 /// makeAnotherReg - This method returns the next register number we haven't
324 /// Long values are handled somewhat specially. They are always allocated
325 /// as pairs of 32 bit integer values. The register number returned is the
326 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
327 /// of the long value.
329 unsigned makeAnotherReg(const Type *Ty) {
330 assert(dynamic_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()) &&
331 "Current target doesn't have PPC reg info??");
332 const PowerPCRegisterInfo *MRI =
333 static_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo());
334 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
335 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
336 // Create the lower part
337 F->getSSARegMap()->createVirtualRegister(RC);
338 // Create the upper part.
339 return F->getSSARegMap()->createVirtualRegister(RC)-1;
342 // Add the mapping of regnumber => reg class to MachineFunction
343 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
344 return F->getSSARegMap()->createVirtualRegister(RC);
347 /// getReg - This method turns an LLVM value into a register number.
349 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
350 unsigned getReg(Value *V) {
351 // Just append to the end of the current bb.
352 MachineBasicBlock::iterator It = BB->end();
353 return getReg(V, BB, It);
355 unsigned getReg(Value *V, MachineBasicBlock *MBB,
356 MachineBasicBlock::iterator IPt);
358 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
359 /// that is to be statically allocated with the initial stack frame
361 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
365 /// dyn_castFixedAlloca - If the specified value is a fixed size alloca
366 /// instruction in the entry block, return it. Otherwise, return a null
368 static AllocaInst *dyn_castFixedAlloca(Value *V) {
369 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
370 BasicBlock *BB = AI->getParent();
371 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
377 /// getReg - This method turns an LLVM value into a register number.
379 unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
380 MachineBasicBlock::iterator IPt) {
381 // If this operand is a constant, emit the code to copy the constant into
382 // the register here...
384 if (Constant *C = dyn_cast<Constant>(V)) {
385 unsigned Reg = makeAnotherReg(V->getType());
386 copyConstantToRegister(MBB, IPt, C, Reg);
388 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
389 // GV is located at PC + distance
390 unsigned CurPC = makeAnotherReg(Type::IntTy);
391 unsigned Reg1 = makeAnotherReg(V->getType());
392 unsigned Reg2 = makeAnotherReg(V->getType());
393 // Move PC to destination reg
394 BuildMI(*MBB, IPt, PPC32::MovePCtoLR, 0, CurPC);
395 // Move value at PC + distance into return reg
396 BuildMI(*MBB, IPt, PPC32::LOADHiAddr, 2, Reg1).addReg(CurPC)
397 .addGlobalAddress(GV);
398 BuildMI(*MBB, IPt, PPC32::LOADLoAddr, 2, Reg2).addReg(Reg1)
399 .addGlobalAddress(GV);
401 } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
402 // Do not emit noop casts at all.
403 if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
404 return getReg(CI->getOperand(0), MBB, IPt);
405 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
406 unsigned Reg = makeAnotherReg(V->getType());
407 unsigned FI = getFixedSizedAllocaFI(AI);
408 addFrameReference(BuildMI(*MBB, IPt, PPC32::ADDI, 2, Reg), FI, 0, false);
412 unsigned &Reg = RegMap[V];
414 Reg = makeAnotherReg(V->getType());
421 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
422 /// that is to be statically allocated with the initial stack frame
424 unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
425 // Already computed this?
426 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
427 if (I != AllocaMap.end() && I->first == AI) return I->second;
429 const Type *Ty = AI->getAllocatedType();
430 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
431 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
432 TySize *= CUI->getValue(); // Get total allocated size...
433 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
435 // Create a new stack object using the frame manager...
436 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
437 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
442 /// copyConstantToRegister - Output the instructions required to put the
443 /// specified constant into the specified register.
445 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
446 MachineBasicBlock::iterator IP,
447 Constant *C, unsigned R) {
448 if (C->getType()->isIntegral()) {
449 unsigned Class = getClassB(C->getType());
451 if (Class == cLong) {
452 // Copy the value into the register pair.
453 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
454 unsigned hiTmp = makeAnotherReg(Type::IntTy);
455 unsigned loTmp = makeAnotherReg(Type::IntTy);
456 BuildMI(*MBB, IP, PPC32::ADDIS, 2, loTmp).addReg(PPC32::R0)
458 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(loTmp)
459 .addImm((Val >> 32) & 0xFFFF);
460 BuildMI(*MBB, IP, PPC32::ADDIS, 2, hiTmp).addReg(PPC32::R0)
461 .addImm((Val >> 16) & 0xFFFF);
462 BuildMI(*MBB, IP, PPC32::ORI, 2, R+1).addReg(hiTmp).addImm(Val & 0xFFFF);
466 assert(Class <= cInt && "Type not handled yet!");
468 if (C->getType() == Type::BoolTy) {
469 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0)
470 .addImm(C == ConstantBool::True);
471 } else if (Class == cByte || Class == cShort) {
472 ConstantInt *CI = cast<ConstantInt>(C);
473 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0)
474 .addImm(CI->getRawValue());
476 ConstantInt *CI = cast<ConstantInt>(C);
477 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
478 if (TheVal < 32768 && TheVal >= -32768) {
479 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0)
480 .addImm(CI->getRawValue());
482 unsigned TmpReg = makeAnotherReg(Type::IntTy);
483 BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0)
484 .addImm(CI->getRawValue() >> 16);
485 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(TmpReg)
486 .addImm(CI->getRawValue() & 0xFFFF);
489 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
490 // We need to spill the constant to memory...
491 MachineConstantPool *CP = F->getConstantPool();
492 unsigned CPI = CP->getConstantPoolIndex(CFP);
493 const Type *Ty = CFP->getType();
495 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
496 unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
497 addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 2, R), CPI);
498 } else if (isa<ConstantPointerNull>(C)) {
499 // Copy zero (null pointer) to the register.
500 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(0);
501 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
502 BuildMI(*MBB, IP, PPC32::ADDIS, 2, R).addReg(PPC32::R0)
503 .addGlobalAddress(CPR->getValue());
504 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(PPC32::R0)
505 .addGlobalAddress(CPR->getValue());
507 std::cerr << "Offending constant: " << C << "\n";
508 assert(0 && "Type not handled yet!");
512 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
513 /// the stack into virtual registers.
515 /// FIXME: When we can calculate which args are coming in via registers
516 /// source them from there instead.
517 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
518 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
519 unsigned GPR_remaining = 8;
520 unsigned FPR_remaining = 13;
521 unsigned GPR_idx = 0, FPR_idx = 0;
522 static const unsigned GPR[] = {
523 PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
524 PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
526 static const unsigned FPR[] = {
527 PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4, PPC32::F5, PPC32::F6, PPC32::F7,
528 PPC32::F8, PPC32::F9, PPC32::F10, PPC32::F11, PPC32::F12, PPC32::F13
531 MachineFrameInfo *MFI = F->getFrameInfo();
533 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
534 bool ArgLive = !I->use_empty();
535 unsigned Reg = ArgLive ? getReg(*I) : 0;
536 int FI; // Frame object index
538 switch (getClassB(I->getType())) {
541 FI = MFI->CreateFixedObject(1, ArgOffset);
542 if (GPR_remaining > 0) {
543 BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
544 .addReg(GPR[GPR_idx]);
546 addFrameReference(BuildMI(BB, PPC32::LBZ, 2, Reg), FI);
552 FI = MFI->CreateFixedObject(2, ArgOffset);
553 if (GPR_remaining > 0) {
554 BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
555 .addReg(GPR[GPR_idx]);
557 addFrameReference(BuildMI(BB, PPC32::LHZ, 2, Reg), FI);
563 FI = MFI->CreateFixedObject(4, ArgOffset);
564 if (GPR_remaining > 0) {
565 BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
566 .addReg(GPR[GPR_idx]);
568 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
574 FI = MFI->CreateFixedObject(8, ArgOffset);
575 if (GPR_remaining > 1) {
576 BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
577 .addReg(GPR[GPR_idx]);
578 BuildMI(BB, PPC32::OR, 2, Reg+1).addReg(GPR[GPR_idx+1])
579 .addReg(GPR[GPR_idx+1]);
581 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
582 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg+1), FI, 4);
585 ArgOffset += 4; // longs require 4 additional bytes
586 if (GPR_remaining > 1) {
587 GPR_remaining--; // uses up 2 GPRs
594 if (I->getType() == Type::FloatTy) {
596 FI = MFI->CreateFixedObject(4, ArgOffset);
599 FI = MFI->CreateFixedObject(8, ArgOffset);
601 if (FPR_remaining > 0) {
602 BuildMI(BB, PPC32::FMR, 1, Reg).addReg(FPR[FPR_idx]);
606 addFrameReference(BuildMI(BB, Opcode, 2, Reg), FI);
609 if (I->getType() == Type::DoubleTy) {
610 ArgOffset += 4; // doubles require 4 additional bytes
611 if (GPR_remaining > 0) {
612 GPR_remaining--; // uses up 2 GPRs
618 assert(0 && "Unhandled argument type!");
620 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
621 if (GPR_remaining > 0) {
622 GPR_remaining--; // uses up 2 GPRs
627 // If the function takes variable number of arguments, add a frame offset for
628 // the start of the first vararg value... this is used to expand
630 if (Fn.getFunctionType()->isVarArg())
631 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
635 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
636 /// because we have to generate our sources into the source basic blocks, not
639 void ISel::SelectPHINodes() {
640 const TargetInstrInfo &TII = *TM.getInstrInfo();
641 const Function &LF = *F->getFunction(); // The LLVM function...
642 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
643 const BasicBlock *BB = I;
644 MachineBasicBlock &MBB = *MBBMap[I];
646 // Loop over all of the PHI nodes in the LLVM basic block...
647 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
648 for (BasicBlock::const_iterator I = BB->begin();
649 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
651 // Create a new machine instr PHI node, and insert it.
652 unsigned PHIReg = getReg(*PN);
653 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
654 PPC32::PHI, PN->getNumOperands(), PHIReg);
656 MachineInstr *LongPhiMI = 0;
657 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
658 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
659 PPC32::PHI, PN->getNumOperands(), PHIReg+1);
661 // PHIValues - Map of blocks to incoming virtual registers. We use this
662 // so that we only initialize one incoming value for a particular block,
663 // even if the block has multiple entries in the PHI node.
665 std::map<MachineBasicBlock*, unsigned> PHIValues;
667 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
668 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
670 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
671 PHIValues.lower_bound(PredMBB);
673 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
674 // We already inserted an initialization of the register for this
675 // predecessor. Recycle it.
676 ValReg = EntryIt->second;
679 // Get the incoming value into a virtual register.
681 Value *Val = PN->getIncomingValue(i);
683 // If this is a constant or GlobalValue, we may have to insert code
684 // into the basic block to compute it into a virtual register.
685 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
686 isa<GlobalValue>(Val)) {
687 // Simple constants get emitted at the end of the basic block,
688 // before any terminator instructions. We "know" that the code to
689 // move a constant into a register will never clobber any flags.
690 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
692 // Because we don't want to clobber any values which might be in
693 // physical registers with the computation of this constant (which
694 // might be arbitrarily complex if it is a constant expression),
695 // just insert the computation at the top of the basic block.
696 MachineBasicBlock::iterator PI = PredMBB->begin();
698 // Skip over any PHI nodes though!
699 while (PI != PredMBB->end() && PI->getOpcode() == PPC32::PHI)
702 ValReg = getReg(Val, PredMBB, PI);
705 // Remember that we inserted a value for this PHI for this predecessor
706 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
709 PhiMI->addRegOperand(ValReg);
710 PhiMI->addMachineBasicBlockOperand(PredMBB);
712 LongPhiMI->addRegOperand(ValReg+1);
713 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
717 // Now that we emitted all of the incoming values for the PHI node, make
718 // sure to reposition the InsertPoint after the PHI that we just added.
719 // This is needed because we might have inserted a constant into this
720 // block, right after the PHI's which is before the old insert point!
721 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
728 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
729 // it into the conditional branch or select instruction which is the only user
730 // of the cc instruction. This is the case if the conditional branch is the
731 // only user of the setcc, and if the setcc is in the same basic block as the
732 // conditional branch. We also don't handle long arguments below, so we reject
733 // them here as well.
735 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
736 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
737 if (SCI->hasOneUse()) {
738 Instruction *User = cast<Instruction>(SCI->use_back());
739 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
740 SCI->getParent() == User->getParent() &&
741 (getClassB(SCI->getOperand(0)->getType()) != cLong ||
742 SCI->getOpcode() == Instruction::SetEQ ||
743 SCI->getOpcode() == Instruction::SetNE))
749 // Return a fixed numbering for setcc instructions which does not depend on the
750 // order of the opcodes.
752 static unsigned getSetCCNumber(unsigned Opcode) {
754 default: assert(0 && "Unknown setcc instruction!");
755 case Instruction::SetEQ: return 0;
756 case Instruction::SetNE: return 1;
757 case Instruction::SetLT: return 2;
758 case Instruction::SetGE: return 3;
759 case Instruction::SetGT: return 4;
760 case Instruction::SetLE: return 5;
764 static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
766 default: assert(0 && "Unknown setcc instruction!");
767 case Instruction::SetEQ: return PPC32::BEQ;
768 case Instruction::SetNE: return PPC32::BNE;
769 case Instruction::SetLT: return PPC32::BLT;
770 case Instruction::SetGE: return PPC32::BGE;
771 case Instruction::SetGT: return PPC32::BGT;
772 case Instruction::SetLE: return PPC32::BLE;
776 static unsigned invertPPCBranchOpcode(unsigned Opcode) {
778 default: assert(0 && "Unknown PPC32 branch opcode!");
779 case PPC32::BEQ: return PPC32::BNE;
780 case PPC32::BNE: return PPC32::BEQ;
781 case PPC32::BLT: return PPC32::BGE;
782 case PPC32::BGE: return PPC32::BLT;
783 case PPC32::BGT: return PPC32::BLE;
784 case PPC32::BLE: return PPC32::BGT;
788 /// emitUCOM - emits an unordered FP compare.
789 void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
790 unsigned LHS, unsigned RHS) {
791 BuildMI(*MBB, IP, PPC32::FCMPU, 2, PPC32::CR0).addReg(LHS).addReg(RHS);
794 // EmitComparison - This function emits a comparison of the two operands,
795 // returning the extended setcc code to use.
796 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
797 MachineBasicBlock *MBB,
798 MachineBasicBlock::iterator IP) {
799 // The arguments are already supposed to be of the same type.
800 const Type *CompTy = Op0->getType();
801 unsigned Class = getClassB(CompTy);
802 unsigned Op0r = getReg(Op0, MBB, IP);
804 // Special case handling of: cmp R, i
805 if (isa<ConstantPointerNull>(Op1)) {
806 BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
807 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
808 if (Class == cByte || Class == cShort || Class == cInt) {
809 unsigned Op1v = CI->getRawValue();
811 // Mask off any upper bits of the constant, if there are any...
812 Op1v &= (1ULL << (8 << Class)) - 1;
814 // Compare immediate or promote to reg?
816 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMPI : PPC32::CMPLI, 3,
817 PPC32::CR0).addImm(0).addReg(Op0r).addImm(Op1v);
819 unsigned Op1r = getReg(Op1, MBB, IP);
820 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 3,
821 PPC32::CR0).addImm(0).addReg(Op0r).addReg(Op1r);
825 assert(Class == cLong && "Unknown integer class!");
826 unsigned LowCst = CI->getRawValue();
827 unsigned HiCst = CI->getRawValue() >> 32;
828 if (OpNum < 2) { // seteq, setne
829 unsigned LoTmp = Op0r;
831 unsigned LoLow = makeAnotherReg(Type::IntTy);
832 unsigned LoTmp = makeAnotherReg(Type::IntTy);
833 BuildMI(*MBB, IP, PPC32::XORI, 2, LoLow).addReg(Op0r).addImm(LowCst);
834 BuildMI(*MBB, IP, PPC32::XORIS, 2, LoTmp).addReg(LoLow)
835 .addImm(LowCst >> 16);
837 unsigned HiTmp = Op0r+1;
839 unsigned HiLow = makeAnotherReg(Type::IntTy);
840 unsigned HiTmp = makeAnotherReg(Type::IntTy);
841 BuildMI(*MBB, IP, PPC32::XORI, 2, HiLow).addReg(Op0r+1).addImm(HiCst);
842 BuildMI(*MBB, IP, PPC32::XORIS, 2, HiTmp).addReg(HiLow)
843 .addImm(HiCst >> 16);
845 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
846 BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
847 //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
850 // FIXME: Not Yet Implemented
851 std::cerr << "EmitComparison unimplemented: Opnum >= 2\n";
858 unsigned Op1r = getReg(Op1, MBB, IP);
860 default: assert(0 && "Unknown type class!");
864 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 2,
865 PPC32::CR0).addReg(Op0r).addReg(Op1r);
869 emitUCOM(MBB, IP, Op0r, Op1r);
873 if (OpNum < 2) { // seteq, setne
874 unsigned LoTmp = makeAnotherReg(Type::IntTy);
875 unsigned HiTmp = makeAnotherReg(Type::IntTy);
876 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
877 BuildMI(*MBB, IP, PPC32::XOR, 2, LoTmp).addReg(Op0r).addReg(Op1r);
878 BuildMI(*MBB, IP, PPC32::XOR, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
879 BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
880 //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
881 break; // Allow the sete or setne to be generated from flags set by OR
883 // FIXME: Not Yet Implemented
884 std::cerr << "EmitComparison (cLong) unimplemented: Opnum >= 2\n";
892 /// visitSetCondInst - emit code to calculate the condition via
893 /// EmitComparison(), and possibly store a 0 or 1 to a register as a result
895 void ISel::visitSetCondInst(SetCondInst &I) {
896 if (canFoldSetCCIntoBranchOrSelect(&I))
899 unsigned Op0Reg = getReg(I.getOperand(0));
900 unsigned Op1Reg = getReg(I.getOperand(1));
901 unsigned DestReg = getReg(I);
902 unsigned OpNum = I.getOpcode();
903 const Type *Ty = I.getOperand (0)->getType();
905 EmitComparison(OpNum, I.getOperand(0), I.getOperand(1), BB, BB->end());
907 unsigned Opcode = getPPCOpcodeForSetCCNumber(OpNum);
908 MachineBasicBlock *thisMBB = BB;
909 const BasicBlock *LLVM_BB = BB->getBasicBlock();
916 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
917 // if we could insert other, non-terminator instructions after the
918 // bCC. But MBB->getFirstTerminator() can't understand this.
919 MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
920 F->getBasicBlockList().push_back(copy1MBB);
921 BuildMI(BB, Opcode, 2).addReg(PPC32::CR0).addMBB(copy1MBB);
922 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
923 F->getBasicBlockList().push_back(copy0MBB);
924 BuildMI(BB, PPC32::B, 1).addMBB(copy0MBB);
925 // Update machine-CFG edges
926 BB->addSuccessor(copy1MBB);
927 BB->addSuccessor(copy0MBB);
930 // %FalseValue = li 0
933 unsigned FalseValue = makeAnotherReg(I.getType());
934 BuildMI(BB, PPC32::LI, 1, FalseValue).addZImm(0);
935 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
936 F->getBasicBlockList().push_back(sinkMBB);
937 BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
938 // Update machine-CFG edges
939 BB->addSuccessor(sinkMBB);
941 DEBUG(std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
942 DEBUG(std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
943 DEBUG(std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
944 DEBUG(std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
950 unsigned TrueValue = makeAnotherReg (I.getType ());
951 BuildMI(BB, PPC32::LI, 1, TrueValue).addZImm(1);
952 BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
953 // Update machine-CFG edges
954 BB->addSuccessor(sinkMBB);
957 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
960 BuildMI(BB, PPC32::PHI, 4, DestReg).addReg(FalseValue)
961 .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
964 void ISel::visitSelectInst(SelectInst &SI) {
965 unsigned DestReg = getReg(SI);
966 MachineBasicBlock::iterator MII = BB->end();
967 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
968 SI.getFalseValue(), DestReg);
971 /// emitSelect - Common code shared between visitSelectInst and the constant
972 /// expression support.
973 /// FIXME: this is most likely broken in one or more ways. Namely, PowerPC has
974 /// no select instruction. FSEL only works for comparisons against zero.
975 void ISel::emitSelectOperation(MachineBasicBlock *MBB,
976 MachineBasicBlock::iterator IP,
977 Value *Cond, Value *TrueVal, Value *FalseVal,
979 unsigned SelectClass = getClassB(TrueVal->getType());
981 unsigned TrueReg = getReg(TrueVal, MBB, IP);
982 unsigned FalseReg = getReg(FalseVal, MBB, IP);
984 if (TrueReg == FalseReg) {
985 if (SelectClass == cFP) {
986 BuildMI(*MBB, IP, PPC32::FMR, 1, DestReg).addReg(TrueReg);
988 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TrueReg).addReg(TrueReg);
991 if (SelectClass == cLong)
992 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TrueReg+1)
997 unsigned CondReg = getReg(Cond, MBB, IP);
998 unsigned numZeros = makeAnotherReg(Type::IntTy);
999 unsigned falseHi = makeAnotherReg(Type::IntTy);
1000 unsigned falseAll = makeAnotherReg(Type::IntTy);
1001 unsigned trueAll = makeAnotherReg(Type::IntTy);
1002 unsigned Temp1 = makeAnotherReg(Type::IntTy);
1003 unsigned Temp2 = makeAnotherReg(Type::IntTy);
1005 BuildMI(*MBB, IP, PPC32::CNTLZW, 1, numZeros).addReg(CondReg);
1006 BuildMI(*MBB, IP, PPC32::RLWINM, 4, falseHi).addReg(numZeros).addImm(26)
1007 .addImm(0).addImm(0);
1008 BuildMI(*MBB, IP, PPC32::SRAWI, 2, falseAll).addReg(falseHi).addImm(31);
1009 BuildMI(*MBB, IP, PPC32::NOR, 2, trueAll).addReg(falseAll).addReg(falseAll);
1010 BuildMI(*MBB, IP, PPC32::AND, 2, Temp1).addReg(TrueReg).addReg(trueAll);
1011 BuildMI(*MBB, IP, PPC32::AND, 2, Temp2).addReg(FalseReg).addReg(falseAll);
1012 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Temp1).addReg(Temp2);
1014 if (SelectClass == cLong) {
1015 unsigned Temp3 = makeAnotherReg(Type::IntTy);
1016 unsigned Temp4 = makeAnotherReg(Type::IntTy);
1017 BuildMI(*MBB, IP, PPC32::AND, 2, Temp3).addReg(TrueReg+1).addReg(trueAll);
1018 BuildMI(*MBB, IP, PPC32::AND, 2, Temp4).addReg(FalseReg+1).addReg(falseAll);
1019 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(Temp3).addReg(Temp4);
1027 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1028 /// operand, in the specified target register.
1030 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1031 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
1033 Value *Val = VR.Val;
1034 const Type *Ty = VR.Ty;
1036 if (Constant *C = dyn_cast<Constant>(Val)) {
1037 Val = ConstantExpr::getCast(C, Type::IntTy);
1041 // If this is a simple constant, just emit a load directly to avoid the copy
1042 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1043 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1045 if (TheVal < 32768 && TheVal >= -32768) {
1046 BuildMI(BB, PPC32::ADDI, 2, targetReg).addReg(PPC32::R0).addImm(TheVal);
1048 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1049 BuildMI(BB, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0)
1050 .addImm(TheVal >> 16);
1051 BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(TmpReg)
1052 .addImm(TheVal & 0xFFFF);
1058 // Make sure we have the register number for this value...
1059 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1061 switch (getClassB(Ty)) {
1063 // Extend value into target register (8->32)
1065 BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1066 .addZImm(24).addZImm(31);
1068 BuildMI(BB, PPC32::EXTSB, 1, targetReg).addReg(Reg);
1071 // Extend value into target register (16->32)
1073 BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1074 .addZImm(16).addZImm(31);
1076 BuildMI(BB, PPC32::EXTSH, 1, targetReg).addReg(Reg);
1079 // Move value into target register (32->32)
1080 BuildMI(BB, PPC32::OR, 2, targetReg).addReg(Reg).addReg(Reg);
1083 assert(0 && "Unpromotable operand class in promote32");
1087 /// visitReturnInst - implemented with BLR
1089 void ISel::visitReturnInst(ReturnInst &I) {
1090 // Only do the processing if this is a non-void return
1091 if (I.getNumOperands() > 0) {
1092 Value *RetVal = I.getOperand(0);
1093 switch (getClassB(RetVal->getType())) {
1094 case cByte: // integral return values: extend or move into r3 and return
1097 promote32(PPC32::R3, ValueRecord(RetVal));
1099 case cFP: { // Floats & Doubles: Return in f1
1100 unsigned RetReg = getReg(RetVal);
1101 BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
1105 unsigned RetReg = getReg(RetVal);
1106 BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
1107 BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
1111 visitInstruction(I);
1114 BuildMI(BB, PPC32::BLR, 1).addImm(0);
1117 // getBlockAfter - Return the basic block which occurs lexically after the
1119 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1120 Function::iterator I = BB; ++I; // Get iterator to next block
1121 return I != BB->getParent()->end() ? &*I : 0;
1124 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1125 /// that since code layout is frozen at this point, that if we are trying to
1126 /// jump to a block that is the immediate successor of the current block, we can
1127 /// just make a fall-through (but we don't currently).
1129 void ISel::visitBranchInst(BranchInst &BI) {
1130 // Update machine-CFG edges
1131 BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
1132 if (BI.isConditional())
1133 BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
1135 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1137 if (!BI.isConditional()) { // Unconditional branch?
1138 if (BI.getSuccessor(0) != NextBB)
1139 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1143 // See if we can fold the setcc into the branch itself...
1144 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1146 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1147 // computed some other way...
1148 unsigned condReg = getReg(BI.getCondition());
1149 BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR1).addImm(0).addReg(condReg)
1151 if (BI.getSuccessor(1) == NextBB) {
1152 if (BI.getSuccessor(0) != NextBB)
1153 BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
1154 .addMBB(MBBMap[BI.getSuccessor(0)]);
1156 BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
1157 .addMBB(MBBMap[BI.getSuccessor(1)]);
1159 if (BI.getSuccessor(0) != NextBB)
1160 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1165 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1166 unsigned Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
1167 MachineBasicBlock::iterator MII = BB->end();
1168 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1170 if (BI.getSuccessor(0) != NextBB) {
1171 BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
1172 .addMBB(MBBMap[BI.getSuccessor(0)]);
1173 if (BI.getSuccessor(1) != NextBB)
1174 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1176 // Change to the inverse condition...
1177 if (BI.getSuccessor(1) != NextBB) {
1178 Opcode = invertPPCBranchOpcode(Opcode);
1179 BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
1180 .addMBB(MBBMap[BI.getSuccessor(1)]);
1186 /// doCall - This emits an abstract call instruction, setting up the arguments
1187 /// and the return value as appropriate. For the actual function call itself,
1188 /// it inserts the specified CallMI instruction into the stream.
1190 /// FIXME: See Documentation at the following URL for "correct" behavior
1191 /// <http://developer.apple.com/documentation/DeveloperTools/Conceptual/MachORuntime/2rt_powerpc_abi/chapter_9_section_5.html>
1192 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1193 const std::vector<ValueRecord> &Args, bool isVarArg) {
1194 // Count how many bytes are to be pushed on the stack...
1195 unsigned NumBytes = 0;
1197 if (!Args.empty()) {
1198 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1199 switch (getClassB(Args[i].Ty)) {
1200 case cByte: case cShort: case cInt:
1201 NumBytes += 4; break;
1203 NumBytes += 8; break;
1205 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1207 default: assert(0 && "Unknown class!");
1210 // Adjust the stack pointer for the new arguments...
1211 BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1213 // Arguments go on the stack in reverse order, as specified by the ABI.
1214 unsigned ArgOffset = 0;
1215 int GPR_remaining = 8, FPR_remaining = 13;
1216 static const unsigned GPR[] = {
1217 PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
1218 PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
1220 static const unsigned FPR[] = {
1221 PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4, PPC32::F5, PPC32::F6,
1222 PPC32::F7, PPC32::F8, PPC32::F9, PPC32::F10, PPC32::F11, PPC32::F12,
1225 unsigned GPR_idx = 0, FPR_idx = 0;
1227 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1229 switch (getClassB(Args[i].Ty)) {
1232 // Promote arg to 32 bits wide into a temporary register...
1233 ArgReg = makeAnotherReg(Type::UIntTy);
1234 promote32(ArgReg, Args[i]);
1237 if (GPR_remaining > 0) {
1238 BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1241 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
1246 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1249 if (GPR_remaining > 0) {
1250 BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1253 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
1258 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1261 if (GPR_remaining > 1) {
1262 BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1264 BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx + 1]).addReg(ArgReg+1)
1267 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
1269 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg+1).addImm(ArgOffset+4)
1273 ArgOffset += 4; // 8 byte entry, not 4.
1274 GPR_remaining -= 1; // uses up 2 GPRs
1278 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1279 if (Args[i].Ty == Type::FloatTy) {
1281 if (FPR_remaining > 0) {
1282 BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1286 BuildMI(BB, PPC32::STFS, 3).addReg(ArgReg).addImm(ArgOffset)
1289 assert(!isVarArg && "Cannot pass floats to vararg functions!");
1291 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1293 if (FPR_remaining > 0) {
1294 BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1297 // For vararg functions, must pass doubles via int regs as well
1299 BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset)
1301 if (GPR_remaining > 1) {
1302 BuildMI(BB, PPC32::LWZ, 2, GPR[GPR_idx]).addImm(ArgOffset)
1304 BuildMI(BB, PPC32::LWZ, 2, GPR[GPR_idx + 1])
1305 .addImm(ArgOffset+4).addReg(PPC32::R1);
1309 BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset)
1313 ArgOffset += 4; // 8 byte entry, not 4.
1314 GPR_remaining--; // uses up 2 GPRs
1319 default: assert(0 && "Unknown class!");
1326 BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(0);
1329 BB->push_back(CallMI);
1330 BuildMI(BB, PPC32::ADJCALLSTACKUP, 1).addImm(NumBytes);
1332 // If there is a return value, scavenge the result from the location the call
1335 if (Ret.Ty != Type::VoidTy) {
1336 unsigned DestClass = getClassB(Ret.Ty);
1337 switch (DestClass) {
1341 // Integral results are in r3
1342 BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
1344 case cFP: // Floating-point return values live in f1
1345 BuildMI(BB, PPC32::FMR, 1, Ret.Reg).addReg(PPC32::F1);
1347 case cLong: // Long values are in r3:r4
1348 BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
1349 BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R4).addReg(PPC32::R4);
1351 default: assert(0 && "Unknown class!");
1357 /// visitCallInst - Push args on stack and do a procedure call instruction.
1358 void ISel::visitCallInst(CallInst &CI) {
1359 MachineInstr *TheCall;
1360 Function *F = CI.getCalledFunction();
1362 // Is it an intrinsic function call?
1363 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1364 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1368 // Emit a CALL instruction with PC-relative displacement.
1369 TheCall = BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(F, true);
1370 } else { // Emit an indirect call through the CTR
1371 unsigned Reg = getReg(CI.getCalledValue());
1372 BuildMI(PPC32::MTSPR, 2).addZImm(9).addReg(Reg);
1373 TheCall = BuildMI(PPC32::CALLindirect, 1).addZImm(20).addZImm(0);
1376 std::vector<ValueRecord> Args;
1377 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1378 Args.push_back(ValueRecord(CI.getOperand(i)));
1380 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1381 bool isVarArg = F ? F->getFunctionType()->isVarArg() : true;
1382 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args, isVarArg);
1386 /// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
1388 static Value *dyncastIsNan(Value *V) {
1389 if (CallInst *CI = dyn_cast<CallInst>(V))
1390 if (Function *F = CI->getCalledFunction())
1391 if (F->getIntrinsicID() == Intrinsic::isunordered)
1392 return CI->getOperand(1);
1396 /// isOnlyUsedByUnorderedComparisons - Return true if this value is only used by
1397 /// or's whos operands are all calls to the isnan predicate.
1398 static bool isOnlyUsedByUnorderedComparisons(Value *V) {
1399 assert(dyncastIsNan(V) && "The value isn't an isnan call!");
1401 // Check all uses, which will be or's of isnans if this predicate is true.
1402 for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){
1403 Instruction *I = cast<Instruction>(*UI);
1404 if (I->getOpcode() != Instruction::Or) return false;
1405 if (I->getOperand(0) != V && !dyncastIsNan(I->getOperand(0))) return false;
1406 if (I->getOperand(1) != V && !dyncastIsNan(I->getOperand(1))) return false;
1412 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1413 /// function, lowering any calls to unknown intrinsic functions into the
1414 /// equivalent LLVM code.
1416 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1417 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1418 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1419 if (CallInst *CI = dyn_cast<CallInst>(I++))
1420 if (Function *F = CI->getCalledFunction())
1421 switch (F->getIntrinsicID()) {
1422 case Intrinsic::not_intrinsic:
1423 case Intrinsic::vastart:
1424 case Intrinsic::vacopy:
1425 case Intrinsic::vaend:
1426 case Intrinsic::returnaddress:
1427 case Intrinsic::frameaddress:
1428 // FIXME: should lower this ourselves
1429 // case Intrinsic::isunordered:
1430 // We directly implement these intrinsics
1432 case Intrinsic::readio: {
1433 // On PPC, memory operations are in-order. Lower this intrinsic
1434 // into a volatile load.
1435 Instruction *Before = CI->getPrev();
1436 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1437 CI->replaceAllUsesWith(LI);
1438 BB->getInstList().erase(CI);
1441 case Intrinsic::writeio: {
1442 // On PPC, memory operations are in-order. Lower this intrinsic
1443 // into a volatile store.
1444 Instruction *Before = CI->getPrev();
1445 StoreInst *LI = new StoreInst(CI->getOperand(1),
1446 CI->getOperand(2), true, CI);
1447 CI->replaceAllUsesWith(LI);
1448 BB->getInstList().erase(CI);
1452 // All other intrinsic calls we must lower.
1453 Instruction *Before = CI->getPrev();
1454 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1455 if (Before) { // Move iterator to instruction after call
1463 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1464 unsigned TmpReg1, TmpReg2, TmpReg3;
1466 case Intrinsic::vastart:
1467 // Get the address of the first vararg value...
1468 TmpReg1 = getReg(CI);
1469 addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex);
1472 case Intrinsic::vacopy:
1473 TmpReg1 = getReg(CI);
1474 TmpReg2 = getReg(CI.getOperand(1));
1475 BuildMI(BB, PPC32::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
1477 case Intrinsic::vaend: return;
1479 case Intrinsic::returnaddress:
1480 case Intrinsic::frameaddress:
1481 TmpReg1 = getReg(CI);
1482 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1483 if (ID == Intrinsic::returnaddress) {
1484 // Just load the return address
1485 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, TmpReg1),
1486 ReturnAddressIndex);
1488 addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1),
1489 ReturnAddressIndex, -4, false);
1492 // Values other than zero are not implemented yet.
1493 BuildMI(BB, PPC32::ADDI, 2, TmpReg1).addReg(PPC32::R0).addImm(0);
1498 // This may be useful for supporting isunordered
1499 case Intrinsic::isnan:
1500 // If this is only used by 'isunordered' style comparisons, don't emit it.
1501 if (isOnlyUsedByUnorderedComparisons(&CI)) return;
1502 TmpReg1 = getReg(CI.getOperand(1));
1503 emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
1504 TmpReg2 = makeAnotherReg(Type::IntTy);
1505 BuildMI(BB, PPC32::MFCR, TmpReg2);
1506 TmpReg3 = getReg(CI);
1507 BuildMI(BB, PPC32::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
1511 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1515 /// visitSimpleBinary - Implement simple binary operators for integral types...
1516 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1519 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1520 unsigned DestReg = getReg(B);
1521 MachineBasicBlock::iterator MI = BB->end();
1522 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1523 unsigned Class = getClassB(B.getType());
1525 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
1528 /// emitBinaryFPOperation - This method handles emission of floating point
1529 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
1530 void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
1531 MachineBasicBlock::iterator IP,
1532 Value *Op0, Value *Op1,
1533 unsigned OperatorClass, unsigned DestReg) {
1535 // Special case: op Reg, <const fp>
1536 if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1)) {
1537 // Create a constant pool entry for this constant.
1538 MachineConstantPool *CP = F->getConstantPool();
1539 unsigned CPI = CP->getConstantPoolIndex(Op1C);
1540 const Type *Ty = Op1->getType();
1542 static const unsigned OpcodeTab[][4] = {
1543 { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
1544 { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
1547 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1548 unsigned TempReg = makeAnotherReg(Ty);
1549 unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
1550 addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
1552 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1553 unsigned Op0r = getReg(Op0, BB, IP);
1554 BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(TempReg);
1558 // Special case: R1 = op <const fp>, R2
1559 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1560 if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
1562 unsigned op1Reg = getReg(Op1, BB, IP);
1563 BuildMI(*BB, IP, PPC32::FNEG, 1, DestReg).addReg(op1Reg);
1566 // R1 = op CST, R2 --> R1 = opr R2, CST
1568 // Create a constant pool entry for this constant.
1569 MachineConstantPool *CP = F->getConstantPool();
1570 unsigned CPI = CP->getConstantPoolIndex(CFP);
1571 const Type *Ty = CFP->getType();
1573 static const unsigned OpcodeTab[][4] = {
1574 { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
1575 { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
1578 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1579 unsigned TempReg = makeAnotherReg(Ty);
1580 unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
1581 addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
1583 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1584 unsigned Op1r = getReg(Op1, BB, IP);
1585 BuildMI(*BB, IP, Opcode, DestReg).addReg(TempReg).addReg(Op1r);
1590 static const unsigned OpcodeTab[] = {
1591 PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV
1594 unsigned Opcode = OpcodeTab[OperatorClass];
1595 unsigned Op0r = getReg(Op0, BB, IP);
1596 unsigned Op1r = getReg(Op1, BB, IP);
1597 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1600 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1601 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1604 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1605 /// and constant expression support.
1607 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1608 MachineBasicBlock::iterator IP,
1609 Value *Op0, Value *Op1,
1610 unsigned OperatorClass, unsigned DestReg) {
1611 unsigned Class = getClassB(Op0->getType());
1613 // Arithmetic and Bitwise operators
1614 static const unsigned OpcodeTab[] = {
1615 PPC32::ADD, PPC32::SUB, PPC32::AND, PPC32::OR, PPC32::XOR
1617 // Otherwise, code generate the full operation with a constant.
1618 static const unsigned BottomTab[] = {
1619 PPC32::ADDC, PPC32::SUBC, PPC32::AND, PPC32::OR, PPC32::XOR
1621 static const unsigned TopTab[] = {
1622 PPC32::ADDE, PPC32::SUBFE, PPC32::AND, PPC32::OR, PPC32::XOR
1626 assert(OperatorClass < 2 && "No logical ops for FP!");
1627 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
1631 if (Op0->getType() == Type::BoolTy) {
1632 if (OperatorClass == 3)
1633 // If this is an or of two isnan's, emit an FP comparison directly instead
1634 // of or'ing two isnan's together.
1635 if (Value *LHS = dyncastIsNan(Op0))
1636 if (Value *RHS = dyncastIsNan(Op1)) {
1637 unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
1638 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1639 emitUCOM(MBB, IP, Op0Reg, Op1Reg);
1640 BuildMI(*MBB, IP, PPC32::MFCR, TmpReg);
1641 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
1642 .addImm(31).addImm(31);
1647 // sub 0, X -> neg X
1648 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
1649 if (OperatorClass == 1 && CI->isNullValue()) {
1650 unsigned op1Reg = getReg(Op1, MBB, IP);
1651 BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg).addReg(op1Reg);
1653 if (Class == cLong) {
1654 unsigned zeroes = makeAnotherReg(Type::IntTy);
1655 unsigned overflow = makeAnotherReg(Type::IntTy);
1656 unsigned T = makeAnotherReg(Type::IntTy);
1657 BuildMI(*MBB, IP, PPC32::CNTLZW, 1, zeroes).addReg(op1Reg);
1658 BuildMI(*MBB, IP, PPC32::RLWINM, 4, overflow).addReg(zeroes).addImm(27)
1659 .addImm(5).addImm(31);
1660 BuildMI(*MBB, IP, PPC32::ADD, 2, T).addReg(op1Reg+1).addReg(overflow);
1661 BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg+1).addReg(T);
1666 // Special case: op Reg, <const int>
1667 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
1668 unsigned Op0r = getReg(Op0, MBB, IP);
1670 // xor X, -1 -> not X
1671 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1672 BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1673 if (Class == cLong) // Invert the top part too
1674 BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg+1).addReg(Op0r+1)
1679 unsigned Opcode = OpcodeTab[OperatorClass];
1680 unsigned Op1r = getReg(Op1, MBB, IP);
1682 if (Class != cLong) {
1683 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1687 // If the constant is zero in the low 32-bits, just copy the low part
1688 // across and apply the normal 32-bit operation to the high parts. There
1689 // will be no carry or borrow into the top.
1690 if (cast<ConstantInt>(Op1C)->getRawValue() == 0) {
1691 if (OperatorClass != 2) // All but and...
1692 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1694 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1695 BuildMI(*MBB, IP, Opcode, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1699 // If this is a long value and the high or low bits have a special
1700 // property, emit some special cases.
1701 unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
1703 // If this is a logical operation and the top 32-bits are zero, just
1704 // operate on the lower 32.
1705 if (Op1h == 0 && OperatorClass > 1) {
1706 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1707 if (OperatorClass != 2) // All but and
1708 BuildMI(*MBB, IP, PPC32::OR, 2,DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
1710 BuildMI(*MBB, IP, PPC32::ADDI, 2,DestReg+1).addReg(PPC32::R0).addImm(0);
1714 // TODO: We could handle lots of other special cases here, such as AND'ing
1715 // with 0xFFFFFFFF00000000 -> noop, etc.
1717 BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r)
1719 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
1724 unsigned Op0r = getReg(Op0, MBB, IP);
1725 unsigned Op1r = getReg(Op1, MBB, IP);
1727 if (Class != cLong) {
1728 unsigned Opcode = OpcodeTab[OperatorClass];
1729 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1731 BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r)
1733 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
1739 /// doMultiply - Emit appropriate instructions to multiply together the
1740 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1741 /// result should be given as DestTy.
1743 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
1744 unsigned DestReg, const Type *DestTy,
1745 unsigned op0Reg, unsigned op1Reg) {
1746 unsigned Class = getClass(DestTy);
1749 BuildMI(*MBB, MBBI, PPC32::MULHW, 2, DestReg+1).addReg(op0Reg+1)
1754 BuildMI(*MBB, MBBI, PPC32::MULLW, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1757 assert(0 && "doMultiply cannot operate on unknown type!");
1761 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1762 // returns zero when the input is not exactly a power of two.
1763 static unsigned ExactLog2(unsigned Val) {
1764 if (Val == 0 || (Val & (Val-1))) return 0;
1774 /// doMultiplyConst - This function is specialized to efficiently codegen an 8,
1775 /// 16, or 32-bit integer multiply by a constant.
1777 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1778 MachineBasicBlock::iterator IP,
1779 unsigned DestReg, const Type *DestTy,
1780 unsigned op0Reg, unsigned ConstRHS) {
1781 unsigned Class = getClass(DestTy);
1782 // Handle special cases here.
1785 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1788 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(op0Reg).addReg(op0Reg);
1791 BuildMI(*MBB, IP, PPC32::ADD, 2,DestReg).addReg(op0Reg).addReg(op0Reg);
1795 // If the element size is exactly a power of 2, use a shift to get it.
1796 if (unsigned Shift = ExactLog2(ConstRHS)) {
1798 default: assert(0 && "Unknown class for this function!");
1802 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(op0Reg)
1803 .addImm(Shift-1).addImm(0).addImm(31-Shift-1);
1808 // Most general case, emit a normal multiply...
1809 unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
1810 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1811 BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg1).addReg(PPC32::R0)
1812 .addImm(ConstRHS >> 16);
1813 BuildMI(*MBB, IP, PPC32::ORI, 2, TmpReg2).addReg(TmpReg1).addImm(ConstRHS);
1815 // Emit a MUL to multiply the register holding the index by
1816 // elementSize, putting the result in OffsetReg.
1817 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg2);
1820 void ISel::visitMul(BinaryOperator &I) {
1821 unsigned ResultReg = getReg(I);
1823 Value *Op0 = I.getOperand(0);
1824 Value *Op1 = I.getOperand(1);
1826 MachineBasicBlock::iterator IP = BB->end();
1827 emitMultiply(BB, IP, Op0, Op1, ResultReg);
1830 void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
1831 Value *Op0, Value *Op1, unsigned DestReg) {
1832 MachineBasicBlock &BB = *MBB;
1833 TypeClass Class = getClass(Op0->getType());
1835 // Simple scalar multiply?
1836 unsigned Op0Reg = getReg(Op0, &BB, IP);
1841 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1842 unsigned Val = (unsigned)CI->getRawValue(); // Isn't a 64-bit constant
1843 doMultiplyConst(&BB, IP, DestReg, Op0->getType(), Op0Reg, Val);
1845 unsigned Op1Reg = getReg(Op1, &BB, IP);
1846 doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
1850 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
1856 // Long value. We have to do things the hard way...
1857 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1858 unsigned CLow = CI->getRawValue();
1859 unsigned CHi = CI->getRawValue() >> 32;
1862 // If the low part of the constant is all zeros, things are simple.
1863 BuildMI(BB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1864 doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
1868 // Multiply the two low parts
1869 unsigned OverflowReg = 0;
1871 BuildMI(BB, IP, PPC32::OR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
1873 unsigned TmpRegL = makeAnotherReg(Type::UIntTy);
1874 unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
1875 OverflowReg = makeAnotherReg(Type::UIntTy);
1876 BuildMI(BB, IP, PPC32::ADDIS, 2, TmpRegL).addReg(PPC32::R0)
1877 .addImm(CLow >> 16);
1878 BuildMI(BB, IP, PPC32::ORI, 2, Op1RegL).addReg(TmpRegL).addImm(CLow);
1879 BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1RegL);
1880 BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg)
1884 unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
1885 doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
1887 unsigned AHBLplusOverflowReg;
1889 AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1890 BuildMI(BB, IP, PPC32::ADD, 2,
1891 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1893 AHBLplusOverflowReg = AHBLReg;
1897 BuildMI(BB, IP, PPC32::OR, 2, DestReg+1).addReg(AHBLplusOverflowReg)
1898 .addReg(AHBLplusOverflowReg);
1900 unsigned ALBHReg = makeAnotherReg(Type::UIntTy);
1901 doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
1903 BuildMI(BB, IP, PPC32::ADD, 2,
1904 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1909 // General 64x64 multiply
1911 unsigned Op1Reg = getReg(Op1, &BB, IP);
1913 // Multiply the two low parts...
1914 BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
1916 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1917 BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg);
1919 unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
1920 BuildMI(BB, IP, PPC32::MULLW, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1922 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1923 BuildMI(BB, IP, PPC32::ADD, 2, AHBLplusOverflowReg).addReg(AHBLReg)
1924 .addReg(OverflowReg);
1926 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1927 BuildMI(BB, IP, PPC32::MULLW, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1929 BuildMI(BB, IP, PPC32::ADD, 2,
1930 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1934 /// visitDivRem - Handle division and remainder instructions... these
1935 /// instruction both require the same instructions to be generated, they just
1936 /// select the result from a different register. Note that both of these
1937 /// instructions work differently for signed and unsigned operands.
1939 void ISel::visitDivRem(BinaryOperator &I) {
1940 unsigned ResultReg = getReg(I);
1941 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
1943 MachineBasicBlock::iterator IP = BB->end();
1944 emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div,
1948 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1949 MachineBasicBlock::iterator IP,
1950 Value *Op0, Value *Op1, bool isDiv,
1951 unsigned ResultReg) {
1952 const Type *Ty = Op0->getType();
1953 unsigned Class = getClass(Ty);
1955 case cFP: // Floating point divide
1957 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
1959 } else { // Floating point remainder...
1960 unsigned Op0Reg = getReg(Op0, BB, IP);
1961 unsigned Op1Reg = getReg(Op1, BB, IP);
1962 MachineInstr *TheCall =
1963 BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(Func["fmod"], true);
1964 std::vector<ValueRecord> Args;
1965 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1966 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1967 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args, false);
1971 // FIXME: Make sure the module has external function
1972 static const char *Fn[] =
1973 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1974 unsigned Op0Reg = getReg(Op0, BB, IP);
1975 unsigned Op1Reg = getReg(Op1, BB, IP);
1976 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1977 MachineInstr *TheCall =
1978 BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(Func[Fn[NameIdx]], true);
1980 std::vector<ValueRecord> Args;
1981 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1982 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1983 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args, false);
1986 case cByte: case cShort: case cInt:
1987 break; // Small integrals, handled below...
1988 default: assert(0 && "Unknown class!");
1991 // Special case signed division by power of 2.
1993 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
1994 assert(Class != cLong && "This doesn't handle 64-bit divides!");
1995 int V = CI->getValue();
1997 if (V == 1) { // X /s 1 => X
1998 unsigned Op0Reg = getReg(Op0, BB, IP);
1999 BuildMI(*BB, IP, PPC32::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
2003 if (V == -1) { // X /s -1 => -X
2004 unsigned Op0Reg = getReg(Op0, BB, IP);
2005 BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(Op0Reg);
2010 if (V < 0) { // Not a positive power of 2?
2012 isNeg = true; // Maybe it's a negative power of 2.
2014 if (unsigned Log = ExactLog2(V)) {
2016 unsigned Op0Reg = getReg(Op0, BB, IP);
2017 unsigned TmpReg = makeAnotherReg(Op0->getType());
2019 BuildMI(*BB, IP, PPC32::SRAWI,2, TmpReg).addReg(Op0Reg).addImm(Log-1);
2021 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(Op0Reg).addReg(Op0Reg);
2023 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2024 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg2).addReg(TmpReg).addImm(Log)
2025 .addImm(32-Log).addImm(31);
2027 unsigned TmpReg3 = makeAnotherReg(Op0->getType());
2028 BuildMI(*BB, IP, PPC32::ADD, 2, TmpReg3).addReg(Op0Reg).addReg(TmpReg2);
2030 unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
2031 BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg4).addReg(Op0Reg).addImm(Log);
2034 BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(TmpReg4);
2039 unsigned Op0Reg = getReg(Op0, BB, IP);
2040 unsigned Op1Reg = getReg(Op1, BB, IP);
2043 if (Ty->isSigned()) {
2044 BuildMI(*BB, IP, PPC32::DIVW, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2046 BuildMI(*BB, IP,PPC32::DIVWU, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2048 } else { // Remainder
2049 unsigned TmpReg1 = makeAnotherReg(Op0->getType());
2050 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2052 if (Ty->isSigned()) {
2053 BuildMI(*BB, IP, PPC32::DIVW, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
2055 BuildMI(*BB, IP, PPC32::DIVWU, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
2057 BuildMI(*BB, IP, PPC32::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
2058 BuildMI(*BB, IP, PPC32::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
2063 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2064 /// for constant immediate shift values, and for constant immediate
2065 /// shift values equal to 1. Even the general case is sort of special,
2066 /// because the shift amount has to be in CL, not just any old register.
2068 void ISel::visitShiftInst(ShiftInst &I) {
2069 MachineBasicBlock::iterator IP = BB->end ();
2070 emitShiftOperation(BB, IP, I.getOperand (0), I.getOperand (1),
2071 I.getOpcode () == Instruction::Shl, I.getType (),
2075 /// emitShiftOperation - Common code shared between visitShiftInst and
2076 /// constant expression support.
2078 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
2079 MachineBasicBlock::iterator IP,
2080 Value *Op, Value *ShiftAmount, bool isLeftShift,
2081 const Type *ResultTy, unsigned DestReg) {
2082 unsigned SrcReg = getReg (Op, MBB, IP);
2083 bool isSigned = ResultTy->isSigned ();
2084 unsigned Class = getClass (ResultTy);
2086 // Longs, as usual, are handled specially...
2087 if (Class == cLong) {
2088 // If we have a constant shift, we can generate much more efficient code
2089 // than otherwise...
2091 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2092 unsigned Amount = CUI->getValue();
2095 // FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA
2096 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
2097 .addImm(Amount).addImm(0).addImm(31-Amount);
2098 BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg)
2099 .addImm(Amount).addImm(32-Amount).addImm(31);
2100 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2101 .addImm(Amount).addImm(0).addImm(31-Amount);
2103 // FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA
2104 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2105 .addImm(32-Amount).addImm(Amount).addImm(31);
2106 BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1)
2107 .addImm(32-Amount).addImm(0).addImm(Amount-1);
2108 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
2109 .addImm(32-Amount).addImm(Amount).addImm(31);
2111 } else { // Shifting more than 32 bits
2115 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg)
2116 .addImm(Amount).addImm(0).addImm(31-Amount);
2118 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg)
2121 BuildMI(*MBB, IP, PPC32::ADDI, 2,DestReg).addReg(PPC32::R0).addImm(0);
2125 BuildMI(*MBB, IP, PPC32::SRAWI, 2, DestReg).addReg(SrcReg+1)
2128 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg+1)
2129 .addImm(32-Amount).addImm(Amount).addImm(31);
2131 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg+1)
2134 BuildMI(*MBB, IP,PPC32::ADDI,2,DestReg+1).addReg(PPC32::R0).addImm(0);
2138 unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
2139 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
2140 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
2141 unsigned TmpReg4 = makeAnotherReg(Type::IntTy);
2142 unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
2143 unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
2144 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2147 BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
2149 BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg2).addReg(SrcReg+1)
2150 .addReg(ShiftAmountReg);
2151 BuildMI(*MBB, IP, PPC32::SRW, 2,TmpReg3).addReg(SrcReg).addReg(TmpReg1);
2152 BuildMI(*MBB, IP, PPC32::OR, 2,TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
2153 BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
2155 BuildMI(*MBB, IP, PPC32::SLW, 2,TmpReg6).addReg(SrcReg).addReg(TmpReg5);
2156 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TmpReg4)
2158 BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg)
2159 .addReg(ShiftAmountReg);
2162 // FIXME: Unimplemented
2163 // Page C-3 of the PowerPC 32bit Programming Environments Manual
2164 std::cerr << "Unimplemented: signed right shift\n";
2167 BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
2169 BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg2).addReg(SrcReg)
2170 .addReg(ShiftAmountReg);
2171 BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg3).addReg(SrcReg+1)
2173 BuildMI(*MBB, IP, PPC32::OR, 2, TmpReg4).addReg(TmpReg2)
2175 BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
2177 BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg6).addReg(SrcReg+1)
2179 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TmpReg4)
2181 BuildMI(*MBB, IP, PPC32::SRW, 2, DestReg+1).addReg(SrcReg+1)
2182 .addReg(ShiftAmountReg);
2189 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2190 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2191 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2192 unsigned Amount = CUI->getValue();
2195 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2196 .addImm(Amount).addImm(0).addImm(31-Amount);
2199 BuildMI(*MBB, IP, PPC32::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
2201 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2202 .addImm(32-Amount).addImm(Amount).addImm(31);
2205 } else { // The shift amount is non-constant.
2206 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2209 BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg)
2210 .addReg(ShiftAmountReg);
2212 BuildMI(*MBB, IP, isSigned ? PPC32::SRAW : PPC32::SRW, 2, DestReg)
2213 .addReg(SrcReg).addReg(ShiftAmountReg);
2219 /// visitLoadInst - Implement LLVM load instructions
2221 void ISel::visitLoadInst(LoadInst &I) {
2222 static const unsigned Opcodes[] = {
2223 PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS
2225 unsigned Class = getClassB(I.getType());
2226 unsigned Opcode = Opcodes[Class];
2227 if (I.getType() == Type::DoubleTy) Opcode = PPC32::LFD;
2229 unsigned DestReg = getReg(I);
2231 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
2232 unsigned FI = getFixedSizedAllocaFI(AI);
2233 if (Class == cLong) {
2234 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg), FI);
2235 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg+1), FI, 4);
2237 addFrameReference(BuildMI(BB, Opcode, 2, DestReg), FI);
2240 unsigned SrcAddrReg = getReg(I.getOperand(0));
2242 if (Class == cLong) {
2243 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(SrcAddrReg);
2244 BuildMI(BB, PPC32::LWZ, 2, DestReg+1).addImm(4).addReg(SrcAddrReg);
2246 BuildMI(BB, Opcode, 2, DestReg).addImm(0).addReg(SrcAddrReg);
2251 /// visitStoreInst - Implement LLVM store instructions
2253 void ISel::visitStoreInst(StoreInst &I) {
2254 unsigned ValReg = getReg(I.getOperand(0));
2255 unsigned AddressReg = getReg(I.getOperand(1));
2257 const Type *ValTy = I.getOperand(0)->getType();
2258 unsigned Class = getClassB(ValTy);
2260 if (Class == cLong) {
2261 BuildMI(BB, PPC32::STW, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
2262 BuildMI(BB, PPC32::STW, 3).addReg(ValReg+1).addImm(4).addReg(AddressReg);
2266 static const unsigned Opcodes[] = {
2267 PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS
2269 unsigned Opcode = Opcodes[Class];
2270 if (ValTy == Type::DoubleTy) Opcode = PPC32::STFD;
2271 BuildMI(BB, Opcode, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
2275 /// visitCastInst - Here we have various kinds of copying with or without sign
2276 /// extension going on.
2278 void ISel::visitCastInst(CastInst &CI) {
2279 Value *Op = CI.getOperand(0);
2281 unsigned SrcClass = getClassB(Op->getType());
2282 unsigned DestClass = getClassB(CI.getType());
2283 // Noop casts are not emitted: getReg will return the source operand as the
2284 // register to use for any uses of the noop cast.
2285 if (DestClass == SrcClass)
2288 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2289 // of the case are GEP instructions, then the cast does not need to be
2290 // generated explicitly, it will be folded into the GEP.
2291 if (DestClass == cLong && SrcClass == cInt) {
2292 bool AllUsesAreGEPs = true;
2293 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2294 if (!isa<GetElementPtrInst>(*I)) {
2295 AllUsesAreGEPs = false;
2299 // No need to codegen this cast if all users are getelementptr instrs...
2300 if (AllUsesAreGEPs) return;
2303 unsigned DestReg = getReg(CI);
2304 MachineBasicBlock::iterator MI = BB->end();
2305 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2308 /// emitCastOperation - Common code shared between visitCastInst and constant
2309 /// expression cast support.
2311 void ISel::emitCastOperation(MachineBasicBlock *BB,
2312 MachineBasicBlock::iterator IP,
2313 Value *Src, const Type *DestTy,
2315 const Type *SrcTy = Src->getType();
2316 unsigned SrcClass = getClassB(SrcTy);
2317 unsigned DestClass = getClassB(DestTy);
2318 unsigned SrcReg = getReg(Src, BB, IP);
2320 // Implement casts to bool by using compare on the operand followed by set if
2321 // not zero on the result.
2322 if (DestTy == Type::BoolTy) {
2327 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2328 BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg).addImm(-1);
2329 BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
2333 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2334 unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
2335 BuildMI(*BB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
2336 BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1);
2337 BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg2);
2351 std::cerr << "Cast fp-to-bool not implemented!";
2357 // Implement casts between values of the same type class (as determined by
2358 // getClass) by using a register-to-register move.
2359 if (SrcClass == DestClass) {
2360 if (SrcClass <= cInt) {
2361 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2362 } else if (SrcClass == cFP && SrcTy == DestTy) {
2363 BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
2364 } else if (SrcClass == cFP) {
2365 if (SrcTy == Type::FloatTy) { // float -> double
2366 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
2367 BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
2368 } else { // double -> float
2369 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
2370 "Unknown cFP member!");
2371 BuildMI(*BB, IP, PPC32::FRSP, 1, DestReg).addReg(SrcReg);
2373 } else if (SrcClass == cLong) {
2374 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2375 BuildMI(*BB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg+1)
2378 assert(0 && "Cannot handle this type of cast instruction!");
2384 // Handle cast of SMALLER int to LARGER int using a move with sign extension
2385 // or zero extension, depending on whether the source type was signed.
2386 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
2387 SrcClass < DestClass) {
2388 bool isLong = DestClass == cLong;
2389 if (isLong) DestClass = cInt;
2391 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
2392 if (SrcClass < cInt) {
2394 unsigned shift = (SrcClass == cByte) ? 24 : 16;
2395 BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0)
2396 .addImm(shift).addImm(31);
2398 BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH,
2399 1, DestReg).addReg(SrcReg);
2402 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2405 if (isLong) { // Handle upper 32 bits as appropriate...
2406 if (isUnsigned) // Zero out top bits...
2407 BuildMI(*BB, IP, PPC32::ADDI, 2, DestReg+1).addReg(PPC32::R0).addImm(0);
2408 else // Sign extend bottom half...
2409 BuildMI(*BB, IP, PPC32::SRAWI, 2, DestReg+1).addReg(DestReg).addImm(31);
2414 // Special case long -> int ...
2415 if (SrcClass == cLong && DestClass == cInt) {
2416 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2420 // Handle cast of LARGER int to SMALLER int with a clear or sign extend
2421 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
2422 && SrcClass > DestClass) {
2423 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
2425 unsigned shift = (SrcClass == cByte) ? 24 : 16;
2426 BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0)
2427 .addImm(shift).addImm(31);
2429 BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH, 1,
2430 DestReg).addReg(SrcReg);
2435 // Handle casts from integer to floating point now...
2436 if (DestClass == cFP) {
2438 // Emit a library call for long to float conversion
2439 if (SrcClass == cLong) {
2440 std::vector<ValueRecord> Args;
2441 Args.push_back(ValueRecord(SrcReg, SrcTy));
2442 MachineInstr *TheCall =
2443 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("__floatdidf", true);
2444 doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
2448 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2449 switch (SrcTy->getTypeID()) {
2450 case Type::BoolTyID:
2451 case Type::SByteTyID:
2452 BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
2454 case Type::UByteTyID:
2455 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0)
2456 .addImm(24).addImm(31);
2458 case Type::ShortTyID:
2459 BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
2461 case Type::UShortTyID:
2462 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0)
2463 .addImm(16).addImm(31);
2466 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
2468 case Type::UIntTyID:
2469 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
2471 default: // No promotion needed...
2477 // Spill the integer to memory and reload it from there.
2478 // Also spill room for a special conversion constant
2479 int ConstantFrameIndex =
2480 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2482 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2484 unsigned constantHi = makeAnotherReg(Type::IntTy);
2485 unsigned constantLo = makeAnotherReg(Type::IntTy);
2486 unsigned ConstF = makeAnotherReg(Type::DoubleTy);
2487 unsigned TempF = makeAnotherReg(Type::DoubleTy);
2489 if (!SrcTy->isSigned()) {
2490 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0)
2492 BuildMI(*BB, IP, PPC32::ADDI, 2, constantLo).addReg(PPC32::R0).addImm(0);
2493 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2494 ConstantFrameIndex);
2495 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo),
2496 ConstantFrameIndex, 4);
2497 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2499 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(SrcReg),
2501 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF),
2502 ConstantFrameIndex);
2503 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
2504 BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
2506 unsigned TempLo = makeAnotherReg(Type::IntTy);
2507 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0)
2509 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantLo).addReg(PPC32::R0)
2511 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2512 ConstantFrameIndex);
2513 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo),
2514 ConstantFrameIndex, 4);
2515 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2517 BuildMI(*BB, IP, PPC32::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
2518 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(TempLo),
2520 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF),
2521 ConstantFrameIndex);
2522 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
2523 BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF ).addReg(ConstF);
2528 // Handle casts from floating point to integer now...
2529 if (SrcClass == cFP) {
2531 // emit library call
2532 if (DestClass == cLong) {
2533 std::vector<ValueRecord> Args;
2534 Args.push_back(ValueRecord(SrcReg, SrcTy));
2535 MachineInstr *TheCall =
2536 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("__fixdfdi", true);
2537 doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
2542 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2544 // load into 32 bit value, and then truncate as necessary
2545 // FIXME: This is wrong for unsigned dest types
2546 //if (DestTy->isSigned()) {
2547 unsigned TempReg = makeAnotherReg(Type::DoubleTy);
2548 BuildMI(*BB, IP, PPC32::FCTIWZ, 1, TempReg).addReg(SrcReg);
2549 addFrameReference(BuildMI(*BB, IP, PPC32::STFD, 3)
2550 .addReg(TempReg), ValueFrameIdx);
2551 addFrameReference(BuildMI(*BB, IP, PPC32::LWZ, 2, DestReg),
2556 // FIXME: Truncate return value
2560 // Anything we haven't handled already, we can't (yet) handle at all.
2561 assert(0 && "Unhandled cast instruction!");
2565 /// visitVANextInst - Implement the va_next instruction...
2567 void ISel::visitVANextInst(VANextInst &I) {
2568 unsigned VAList = getReg(I.getOperand(0));
2569 unsigned DestReg = getReg(I);
2572 switch (I.getArgType()->getTypeID()) {
2575 assert(0 && "Error: bad type for va_next instruction!");
2577 case Type::PointerTyID:
2578 case Type::UIntTyID:
2582 case Type::ULongTyID:
2583 case Type::LongTyID:
2584 case Type::DoubleTyID:
2589 // Increment the VAList pointer...
2590 BuildMI(BB, PPC32::ADDI, 2, DestReg).addReg(VAList).addImm(Size);
2593 void ISel::visitVAArgInst(VAArgInst &I) {
2594 unsigned VAList = getReg(I.getOperand(0));
2595 unsigned DestReg = getReg(I);
2597 switch (I.getType()->getTypeID()) {
2600 assert(0 && "Error: bad type for va_next instruction!");
2602 case Type::PointerTyID:
2603 case Type::UIntTyID:
2605 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(VAList);
2607 case Type::ULongTyID:
2608 case Type::LongTyID:
2609 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(VAList);
2610 BuildMI(BB, PPC32::LWZ, 2, DestReg+1).addImm(4).addReg(VAList);
2612 case Type::DoubleTyID:
2613 BuildMI(BB, PPC32::LFD, 2, DestReg).addImm(0).addReg(VAList);
2618 /// visitGetElementPtrInst - instruction-select GEP instructions
2620 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2621 unsigned outputReg = getReg(I);
2622 emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(),
2626 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2627 MachineBasicBlock::iterator IP,
2628 Value *Src, User::op_iterator IdxBegin,
2629 User::op_iterator IdxEnd, unsigned TargetReg) {
2630 const TargetData &TD = TM.getTargetData();
2631 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
2632 Src = CPR->getValue();
2634 std::vector<Value*> GEPOps;
2635 GEPOps.resize(IdxEnd-IdxBegin+1);
2637 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2639 std::vector<const Type*> GEPTypes;
2640 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2641 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2643 // Keep emitting instructions until we consume the entire GEP instruction.
2644 while (!GEPOps.empty()) {
2645 if (GEPTypes.empty()) {
2646 // Load the base pointer into a register.
2647 unsigned Reg = getReg(Src, MBB, IP);
2648 BuildMI(*MBB, IP, PPC32::OR, 2, TargetReg).addReg(Reg).addReg(Reg);
2649 break; // we are now done
2651 // It's an array or pointer access: [ArraySize x ElementType].
2652 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2653 Value *idx = GEPOps.back();
2654 GEPOps.pop_back(); // Consume a GEP operand
2655 GEPTypes.pop_back();
2657 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
2658 // operand. Handle this case directly now...
2659 if (CastInst *CI = dyn_cast<CastInst>(idx))
2660 if (CI->getOperand(0)->getType() == Type::IntTy ||
2661 CI->getOperand(0)->getType() == Type::UIntTy)
2662 idx = CI->getOperand(0);
2664 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2665 // must find the size of the pointed-to type (Not coincidentally, the next
2666 // type is the type of the elements in the array).
2667 const Type *ElTy = SqTy->getElementType();
2668 unsigned elementSize = TD.getTypeSize(ElTy);
2670 if (idx == Constant::getNullValue(idx->getType())) {
2671 // GEP with idx 0 is a no-op
2672 } else if (elementSize == 1) {
2673 // If the element size is 1, we don't have to multiply, just add
2674 unsigned idxReg = getReg(idx, MBB, IP);
2675 unsigned Reg = makeAnotherReg(Type::UIntTy);
2676 BuildMI(*MBB, IP, PPC32::ADD, 2,TargetReg).addReg(Reg).addReg(idxReg);
2677 --IP; // Insert the next instruction before this one.
2678 TargetReg = Reg; // Codegen the rest of the GEP into this
2680 unsigned idxReg = getReg(idx, MBB, IP);
2681 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2683 // Make sure we can back the iterator up to point to the first
2684 // instruction emitted.
2685 MachineBasicBlock::iterator BeforeIt = IP;
2686 if (IP == MBB->begin())
2687 BeforeIt = MBB->end();
2690 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2692 // Emit an ADD to add OffsetReg to the basePtr.
2693 unsigned Reg = makeAnotherReg(Type::UIntTy);
2694 BuildMI(*MBB, IP, PPC32::ADD, 2, TargetReg).addReg(Reg).addReg(OffsetReg);
2696 // Step to the first instruction of the multiply.
2697 if (BeforeIt == MBB->end())
2702 TargetReg = Reg; // Codegen the rest of the GEP into this
2707 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2708 /// frame manager, otherwise do it the hard way.
2710 void ISel::visitAllocaInst(AllocaInst &I) {
2711 // If this is a fixed size alloca in the entry block for the function, we
2712 // statically stack allocate the space, so we don't need to do anything here.
2714 if (dyn_castFixedAlloca(&I)) return;
2716 // Find the data size of the alloca inst's getAllocatedType.
2717 const Type *Ty = I.getAllocatedType();
2718 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2720 // Create a register to hold the temporary result of multiplying the type size
2721 // constant by the variable amount.
2722 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2723 unsigned SrcReg1 = getReg(I.getArraySize());
2725 // TotalSizeReg = mul <numelements>, <TypeSize>
2726 MachineBasicBlock::iterator MBBI = BB->end();
2727 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2729 // AddedSize = add <TotalSizeReg>, 15
2730 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2731 BuildMI(BB, PPC32::ADD, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
2733 // AlignedSize = and <AddedSize>, ~15
2734 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2735 BuildMI(BB, PPC32::RLWNM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
2736 .addImm(0).addImm(27);
2738 // Subtract size from stack pointer, thereby allocating some space.
2739 BuildMI(BB, PPC32::SUB, 2, PPC32::R1).addReg(PPC32::R1).addReg(AlignedSize);
2741 // Put a pointer to the space into the result register, by copying
2742 // the stack pointer.
2743 BuildMI(BB, PPC32::OR, 2, getReg(I)).addReg(PPC32::R1).addReg(PPC32::R1);
2745 // Inform the Frame Information that we have just allocated a variable-sized
2747 F->getFrameInfo()->CreateVariableSizedObject();
2750 /// visitMallocInst - Malloc instructions are code generated into direct calls
2751 /// to the library malloc.
2753 void ISel::visitMallocInst(MallocInst &I) {
2754 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2757 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2758 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2760 Arg = makeAnotherReg(Type::UIntTy);
2761 unsigned Op0Reg = getReg(I.getOperand(0));
2762 MachineBasicBlock::iterator MBBI = BB->end();
2763 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2766 std::vector<ValueRecord> Args;
2767 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2768 MachineInstr *TheCall =
2769 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("malloc", true);
2770 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
2774 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2777 void ISel::visitFreeInst(FreeInst &I) {
2778 std::vector<ValueRecord> Args;
2779 Args.push_back(ValueRecord(I.getOperand(0)));
2780 MachineInstr *TheCall =
2781 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("free", true);
2782 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
2785 /// createPPC32SimpleInstructionSelector - This pass converts an LLVM function
2786 /// into a machine code representation is a very simple peep-hole fashion. The
2787 /// generated code sucks but the implementation is nice and simple.
2789 FunctionPass *llvm::createPPCSimpleInstructionSelector(TargetMachine &TM) {
2790 return new ISel(TM);