1 //===- PowerPCInstrInfo.cpp - PowerPC Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PowerPCInstrInfo.h"
16 #include "PowerPCGenInstrInfo.inc"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 PowerPCInstrInfo::PowerPCInstrInfo(bool is64b)
22 : TargetInstrInfo(PowerPCInsts, sizeof(PowerPCInsts)/sizeof(PowerPCInsts[0])),
27 bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI,
29 unsigned& destReg) const {
30 MachineOpCode oc = MI.getOpcode();
31 if (oc == PPC::OR) { // or r1, r2, r2
32 assert(MI.getNumOperands() == 3 &&
33 MI.getOperand(0).isRegister() &&
34 MI.getOperand(1).isRegister() &&
35 MI.getOperand(2).isRegister() &&
36 "invalid PPC OR instruction!");
37 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
38 sourceReg = MI.getOperand(1).getReg();
39 destReg = MI.getOperand(0).getReg();
42 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
43 assert(MI.getNumOperands() == 3 &&
44 MI.getOperand(0).isRegister() &&
45 MI.getOperand(2).isImmediate() &&
46 "invalid PPC ADDI instruction!");
47 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
48 sourceReg = MI.getOperand(1).getReg();
49 destReg = MI.getOperand(0).getReg();
52 } else if (oc == PPC::FMR) { // fmr r1, r2
53 assert(MI.getNumOperands() == 2 &&
54 MI.getOperand(0).isRegister() &&
55 MI.getOperand(1).isRegister() &&
56 "invalid PPC FMR instruction");
57 sourceReg = MI.getOperand(1).getReg();
58 destReg = MI.getOperand(0).getReg();