1 //===- PowerPCRegisterInfo.cpp - PowerPC Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PowerPCRegisterInfo.h"
17 #include "PowerPCInstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetMachineImpls.h"
27 #include "Support/CommandLine.h"
28 #include "Support/Debug.h"
29 #include "Support/STLExtras.h"
32 PowerPCRegisterInfo::PowerPCRegisterInfo()
33 : PowerPCGenRegisterInfo(PPC32::ADJCALLSTACKDOWN,
34 PPC32::ADJCALLSTACKUP) {}
36 static unsigned getIdx(const TargetRegisterClass *RC) {
37 if (RC == PowerPC::GPRCRegisterClass) {
38 switch (RC->getSize()) {
39 default: assert(0 && "Invalid data size!");
44 } else if (RC == PowerPC::FPRCRegisterClass) {
45 switch (RC->getSize()) {
46 default: assert(0 && "Invalid data size!");
51 std::cerr << "Invalid register class to getIdx()!\n";
56 PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
57 MachineBasicBlock::iterator MI,
58 unsigned SrcReg, int FrameIdx,
59 const TargetRegisterClass *RC) const {
60 static const unsigned Opcode[] = {
61 PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS, PPC32::STFD
63 unsigned OC = Opcode[getIdx(RC)];
64 MBB.insert(MI, addFrameReference(BuildMI(OC, 3).addReg(SrcReg),FrameIdx));
68 int PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator MI,
70 unsigned DestReg, int FrameIdx,
71 const TargetRegisterClass *RC) const{
72 static const unsigned Opcode[] = {
73 PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS, PPC32::LFD
75 unsigned OC = Opcode[getIdx(RC)];
76 MBB.insert(MI, addFrameReference(BuildMI(OC, 2, DestReg), FrameIdx));
80 int PowerPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MI,
82 unsigned DestReg, unsigned SrcReg,
83 const TargetRegisterClass *RC) const {
86 if (RC == PowerPC::GPRCRegisterClass) {
87 I = BuildMI(PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
88 } else if (RC == PowerPC::FPRCRegisterClass) {
89 I = BuildMI(PPC32::FMR, 1, DestReg).addReg(SrcReg);
91 std::cerr << "Attempt to copy register that is not GPR or FPR";
98 //===----------------------------------------------------------------------===//
99 // Stack Frame Processing methods
100 //===----------------------------------------------------------------------===//
102 // hasFP - Return true if the specified function should have a dedicated frame
103 // pointer register. This is true if the function has variable sized allocas or
104 // if frame pointer elimination is disabled.
106 static bool hasFP(MachineFunction &MF) {
107 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
110 void PowerPCRegisterInfo::
111 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
112 MachineBasicBlock::iterator I) const {
114 // If we have a frame pointer, turn the adjcallstackdown instruction into a
115 // 'sub r1, r1, <amt>' and the adjcallstackup instruction into 'add r1, r1, <amt>'
116 MachineInstr *Old = I;
117 int Amount = Old->getOperand(0).getImmedValue();
119 // We need to keep the stack aligned properly. To do this, we round the
120 // amount of space needed for the outgoing arguments up to the next
121 // alignment boundary.
122 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
123 Amount = (Amount+Align-1)/Align*Align;
126 if (Old->getOpcode() == PPC32::ADJCALLSTACKDOWN) {
127 New = BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1)
130 assert(Old->getOpcode() == PPC32::ADJCALLSTACKUP);
131 New = BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1)
135 // Replace the pseudo instruction with a new instruction...
144 PowerPCRegisterInfo::eliminateFrameIndex(MachineFunction &MF,
145 MachineBasicBlock::iterator II) const {
147 MachineInstr &MI = *II;
148 while (!MI.getOperand(i).isFrameIndex()) {
150 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
153 int FrameIndex = MI.getOperand(i).getFrameIndex();
155 // This must be part of a four operand memory reference. Replace the
156 // FrameIndex with base register with GPR1.
157 MI.SetMachineOperandReg(i, PPC32::R1);
159 // Take into account whether its an add or mem instruction
162 // Now add the frame object offset to the offset from r1.
163 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
164 MI.getOperand(i).getImmedValue()+4;
167 Offset += MF.getFrameInfo()->getStackSize();
169 MI.SetMachineOperandConst(i-1, MachineOperand::MO_SignExtendedImmed, Offset);
170 DEBUG(std::cerr << "offset = " << Offset << std::endl);
175 PowerPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
180 void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
181 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
182 MachineBasicBlock::iterator MBBI = MBB.begin();
183 MachineFrameInfo *MFI = MF.getFrameInfo();
186 // Get the number of bytes to allocate from the FrameInfo
187 unsigned NumBytes = MFI->getStackSize();
189 if (MFI->hasCalls()) {
190 // When we have no frame pointer, we reserve argument space for call sites
191 // in the function immediately on entry to the current function. This
192 // eliminates the need for add/sub brackets around call sites.
194 NumBytes += MFI->getMaxCallFrameSize();
196 // Round the size to a multiple of the alignment (don't forget the 4 byte
198 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
199 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
201 // Store the incoming LR so it is preserved across calls
202 MI = BuildMI(PPC32::MovePCtoLR, 0, PPC32::LR).addReg(PPC32::LR);
203 MBB.insert(MBBI, MI);
204 MI = BuildMI(PPC32::MFSPR, 1, PPC32::R0).addImm(8);
205 MBB.insert(MBBI, MI);
206 MI = BuildMI(PPC32::STW, 3).addReg(PPC32::R0).addSImm(8).addReg(PPC32::R1);
207 MBB.insert(MBBI, MI);
210 // Update frame info to pretend that this is part of the stack...
211 MFI->setStackSize(NumBytes);
213 // adjust stack pointer: r1 -= numbytes
215 MI = BuildMI(PPC32::STWU, 2, PPC32::R1).addImm(-NumBytes).addReg(PPC32::R1);
216 MBB.insert(MBBI, MI);
220 void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
221 MachineBasicBlock &MBB) const {
222 const MachineFrameInfo *MFI = MF.getFrameInfo();
223 MachineBasicBlock::iterator MBBI = prior(MBB.end());
225 assert(MBBI->getOpcode() == PPC32::BLR &&
226 "Can only insert epilog into returning blocks");
228 // Get the number of bytes allocated from the FrameInfo...
229 unsigned NumBytes = MFI->getStackSize();
231 // adjust stack pointer back: r1 += numbytes
233 MI =BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1).addSImm(NumBytes);
234 MBB.insert(MBBI, MI);
237 // If we have calls, restore the LR value before we branch to it
238 if (MFI->hasCalls()) {
239 MI = BuildMI(PPC32::LWZ, 2, PPC32::R0).addSImm(8).addReg(PPC32::R1);
240 MBB.insert(MBBI, MI);
241 MI = BuildMI(PPC32::MTLR, 1).addReg(PPC32::R0);
242 MBB.insert(MBBI, MI);
246 #include "PowerPCGenRegisterInfo.inc"
248 const TargetRegisterClass*
249 PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
250 switch (Ty->getTypeID()) {
252 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
253 default: assert(0 && "Invalid type to getClass!");
255 case Type::SByteTyID:
256 case Type::UByteTyID:
257 case Type::ShortTyID:
258 case Type::UShortTyID:
261 case Type::PointerTyID: return &GPRCInstance;
263 case Type::FloatTyID:
264 case Type::DoubleTyID: return &FPRCInstance;