1 //===- PowerPCRegisterInfo.cpp - PowerPC Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PowerPCRegisterInfo.h"
17 #include "PowerPCInstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetMachineImpls.h"
27 #include "Support/CommandLine.h"
28 #include "Support/Debug.h"
29 #include "Support/STLExtras.h"
33 PowerPCRegisterInfo::PowerPCRegisterInfo()
34 : PowerPCGenRegisterInfo(PPC32::ADJCALLSTACKDOWN,
35 PPC32::ADJCALLSTACKUP) {}
37 static unsigned getIdx(const TargetRegisterClass *RC) {
38 if (RC == PowerPC::GPRCRegisterClass) {
39 switch (RC->getSize()) {
40 default: assert(0 && "Invalid data size!");
45 } else if (RC == PowerPC::FPRCRegisterClass) {
46 switch (RC->getSize()) {
47 default: assert(0 && "Invalid data size!");
52 std::cerr << "Invalid register class to getIdx()!\n";
57 PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MI,
59 unsigned SrcReg, int FrameIdx,
60 const TargetRegisterClass *RC) const {
61 static const unsigned Opcode[] = {
62 PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS, PPC32::STFD
64 unsigned OC = Opcode[getIdx(RC)];
65 MBB.insert(MI, addFrameReference(BuildMI(OC, 3).addReg(SrcReg),FrameIdx));
69 int PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator MI,
71 unsigned DestReg, int FrameIdx,
72 const TargetRegisterClass *RC) const{
73 static const unsigned Opcode[] = {
74 PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS, PPC32::LFD
76 unsigned OC = Opcode[getIdx(RC)];
77 MBB.insert(MI, addFrameReference(BuildMI(OC, 2, DestReg), FrameIdx));
81 int PowerPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MI,
83 unsigned DestReg, unsigned SrcReg,
84 const TargetRegisterClass *RC) const {
87 if (RC == PowerPC::GPRCRegisterClass) {
88 I = BuildMI(PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
89 } else if (RC == PowerPC::FPRCRegisterClass) {
90 I = BuildMI(PPC32::FMR, 1, DestReg).addReg(SrcReg);
92 std::cerr << "Attempt to copy register that is not GPR or FPR";
99 //===----------------------------------------------------------------------===//
100 // Stack Frame Processing methods
101 //===----------------------------------------------------------------------===//
103 // hasFP - Return true if the specified function should have a dedicated frame
104 // pointer register. This is true if the function has variable sized allocas or
105 // if frame pointer elimination is disabled.
107 static bool hasFP(MachineFunction &MF) {
108 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
111 void PowerPCRegisterInfo::
112 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator I) const {
115 // If we have a frame pointer, turn the adjcallstackdown instruction into a
116 // 'sub r1, r1, <amt>' and the adjcallstackup instruction into
117 // 'add r1, r1, <amt>'
118 MachineInstr *Old = I;
119 int Amount = Old->getOperand(0).getImmedValue();
121 // We need to keep the stack aligned properly. To do this, we round the
122 // amount of space needed for the outgoing arguments up to the next
123 // alignment boundary.
124 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
125 Amount = (Amount+Align-1)/Align*Align;
128 if (Old->getOpcode() == PPC32::ADJCALLSTACKDOWN) {
129 New = BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1)
132 assert(Old->getOpcode() == PPC32::ADJCALLSTACKUP);
133 New = BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1)
137 // Replace the pseudo instruction with a new instruction...
146 PowerPCRegisterInfo::eliminateFrameIndex(MachineFunction &MF,
147 MachineBasicBlock::iterator II) const {
149 MachineInstr &MI = *II;
150 while (!MI.getOperand(i).isFrameIndex()) {
152 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
155 int FrameIndex = MI.getOperand(i).getFrameIndex();
157 // Replace the FrameIndex with base register with GPR1.
158 MI.SetMachineOperandReg(i, PPC32::R1);
160 // Take into account whether it's an add or mem instruction
161 unsigned OffIdx = (i == 2) ? 1 : 2;
162 // Now add the frame object offset to the offset from r1.
163 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
164 MI.getOperand(OffIdx).getImmedValue()+4;
167 Offset += MF.getFrameInfo()->getStackSize();
169 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, Offset);
170 DEBUG(std::cerr << "offset = " << Offset << std::endl);
175 PowerPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
180 void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
181 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
182 MachineBasicBlock::iterator MBBI = MBB.begin();
183 MachineFrameInfo *MFI = MF.getFrameInfo();
186 // Get the number of bytes to allocate from the FrameInfo
187 unsigned NumBytes = MFI->getStackSize();
189 // FIXME: the assembly printer inserts "calls" aka branch-and-link to get the
190 // PC address. We may not know about those calls at this time, so be
192 if (MFI->hasCalls() || true) {
193 // When we have no frame pointer, we reserve argument space for call sites
194 // in the function immediately on entry to the current function. This
195 // eliminates the need for add/sub brackets around call sites.
197 NumBytes += MFI->getMaxCallFrameSize() +
198 24 /* Predefined PowerPC link area */ +
199 // FIXME: must calculate #int regs actually spilled
200 12*4 /* Spilled int regs */ +
201 // FIXME: must calculate #fp regs actually spilled
202 0*8 /* Spilled fp regs */;
204 // Round the size to a multiple of the alignment (don't forget the 4 byte
206 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
207 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
209 // Store the incoming LR so it is preserved across calls
210 MI = BuildMI(PPC32::MFLR, 0, PPC32::R0);
211 MBB.insert(MBBI, MI);
212 MI = BuildMI(PPC32::STMW, 3).addReg(PPC32::R30).addSImm(-8)
214 MBB.insert(MBBI, MI);
215 MI = BuildMI(PPC32::STW, 3).addReg(PPC32::R0).addSImm(8).addReg(PPC32::R1);
216 MBB.insert(MBBI, MI);
219 // Update frame info to pretend that this is part of the stack...
220 MFI->setStackSize(NumBytes);
222 // adjust stack pointer: r1 -= numbytes
224 MI = BuildMI(PPC32::STWU, 2, PPC32::R1).addImm(-NumBytes).addReg(PPC32::R1);
225 MBB.insert(MBBI, MI);
229 void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
230 MachineBasicBlock &MBB) const {
231 const MachineFrameInfo *MFI = MF.getFrameInfo();
232 MachineBasicBlock::iterator MBBI = prior(MBB.end());
234 assert(MBBI->getOpcode() == PPC32::BLR &&
235 "Can only insert epilog into returning blocks");
237 // Get the number of bytes allocated from the FrameInfo...
238 unsigned NumBytes = MFI->getStackSize();
240 // Adjust stack pointer back
241 MI = BuildMI(PPC32::LWZ, 2, PPC32::R1).addImm(0).addReg(PPC32::R1);
242 MBB.insert(MBBI, MI);
244 // If we have calls, restore the LR value before we branch to it
245 // FIXME: the assembly printer inserts "calls" aka branch-and-link to get the
246 // PC address. We may not know about those calls at this time, so be
248 if (MFI->hasCalls() || true) {
249 // Read old LR from stack into R0
250 MI = BuildMI(PPC32::LWZ, 2, PPC32::R0).addSImm(8).addReg(PPC32::R1);
251 MBB.insert(MBBI, MI);
252 MI = BuildMI(PPC32::MTLR, 1).addReg(PPC32::R0);
253 MBB.insert(MBBI, MI);
254 MI = BuildMI(PPC32::LMW, 2, PPC32::R30).addSImm(-8).addReg(PPC32::R1);
255 MBB.insert(MBBI, MI);
259 #include "PowerPCGenRegisterInfo.inc"
261 const TargetRegisterClass*
262 PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
263 switch (Ty->getTypeID()) {
265 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
266 default: assert(0 && "Invalid type to getClass!");
268 case Type::SByteTyID:
269 case Type::UByteTyID:
270 case Type::ShortTyID:
271 case Type::UShortTyID:
274 case Type::PointerTyID: return &GPRCInstance;
276 case Type::FloatTyID:
277 case Type::DoubleTyID: return &FPRCInstance;