1 //===- README.txt - Notes for improving PowerPC-specific code gen ---------===//
5 * implement do-loop -> bdnz transform
6 * Implement __builtin_trap (ISD::TRAP) as 'tw 31, 0, 0' aka 'trap'.
7 * lmw/stmw pass a la arm load store optimizer for prolog/epilog
9 ===-------------------------------------------------------------------------===
11 Support 'update' load/store instructions. These are cracked on the G5, but are
14 With preinc enabled, this:
16 long *%test4(long *%X, long *%dest) {
17 %Y = getelementptr long* %X, int 4
19 store long %A, long* %dest
34 with -sched=list-burr, I get:
43 ===-------------------------------------------------------------------------===
45 We compile the hottest inner loop of viterbi to:
56 bne cr0, LBB1_83 ;bb420.i
58 The CBE manages to produce:
69 This could be much better (bdnz instead of bdz) but it still beats us. If we
70 produced this with bdnz, the loop would be a single dispatch group.
72 ===-------------------------------------------------------------------------===
89 This is effectively a simple form of predication.
91 ===-------------------------------------------------------------------------===
93 Lump the constant pool for each function into ONE pic object, and reference
94 pieces of it as offsets from the start. For functions like this (contrived
95 to have lots of constants obviously):
97 double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
102 lis r2, ha16(.CPI_X_0)
103 lfd f0, lo16(.CPI_X_0)(r2)
104 lis r2, ha16(.CPI_X_1)
105 lfd f2, lo16(.CPI_X_1)(r2)
107 lis r2, ha16(.CPI_X_2)
108 lfd f1, lo16(.CPI_X_2)(r2)
109 lis r2, ha16(.CPI_X_3)
110 lfd f2, lo16(.CPI_X_3)(r2)
114 It would be better to materialize .CPI_X into a register, then use immediates
115 off of the register to avoid the lis's. This is even more important in PIC
118 Note that this (and the static variable version) is discussed here for GCC:
119 http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
121 Here's another example (the sgn function):
122 double testf(double a) {
123 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
126 it produces a BB like this:
128 lis r2, ha16(LCPI1_0)
129 lfs f0, lo16(LCPI1_0)(r2)
130 lis r2, ha16(LCPI1_1)
131 lis r3, ha16(LCPI1_2)
132 lfs f2, lo16(LCPI1_2)(r3)
133 lfs f3, lo16(LCPI1_1)(r2)
138 ===-------------------------------------------------------------------------===
140 PIC Code Gen IPO optimization:
142 Squish small scalar globals together into a single global struct, allowing the
143 address of the struct to be CSE'd, avoiding PIC accesses (also reduces the size
144 of the GOT on targets with one).
146 Note that this is discussed here for GCC:
147 http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
149 ===-------------------------------------------------------------------------===
151 Implement Newton-Rhapson method for improving estimate instructions to the
152 correct accuracy, and implementing divide as multiply by reciprocal when it has
153 more than one use. Itanium will want this too.
155 ===-------------------------------------------------------------------------===
159 int %f1(int %a, int %b) {
160 %tmp.1 = and int %a, 15 ; <int> [#uses=1]
161 %tmp.3 = and int %b, 240 ; <int> [#uses=1]
162 %tmp.4 = or int %tmp.3, %tmp.1 ; <int> [#uses=1]
166 without a copy. We make this currently:
169 rlwinm r2, r4, 0, 24, 27
170 rlwimi r2, r3, 0, 28, 31
174 The two-addr pass or RA needs to learn when it is profitable to commute an
175 instruction to avoid a copy AFTER the 2-addr instruction. The 2-addr pass
176 currently only commutes to avoid inserting a copy BEFORE the two addr instr.
178 ===-------------------------------------------------------------------------===
180 Compile offsets from allocas:
183 %X = alloca { int, int }
184 %Y = getelementptr {int,int}* %X, int 0, uint 1
188 into a single add, not two:
195 --> important for C++.
197 ===-------------------------------------------------------------------------===
199 No loads or stores of the constants should be needed:
201 struct foo { double X, Y; };
202 void xxx(struct foo F);
203 void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }
205 ===-------------------------------------------------------------------------===
207 Darwin Stub LICM optimization:
213 Have to go through an indirect stub if bar is external or linkonce. It would
214 be better to compile it as:
219 which only computes the address of bar once (instead of each time through the
220 stub). This is Darwin specific and would have to be done in the code generator.
221 Probably not a win on x86.
223 ===-------------------------------------------------------------------------===
225 Simple IPO for argument passing, change:
226 void foo(int X, double Y, int Z) -> void foo(int X, int Z, double Y)
228 the Darwin ABI specifies that any integer arguments in the first 32 bytes worth
229 of arguments get assigned to r3 through r10. That is, if you have a function
230 foo(int, double, int) you get r3, f1, r6, since the 64 bit double ate up the
231 argument bytes for r4 and r5. The trick then would be to shuffle the argument
232 order for functions we can internalize so that the maximum number of
233 integers/pointers get passed in regs before you see any of the fp arguments.
235 Instead of implementing this, it would actually probably be easier to just
236 implement a PPC fastcc, where we could do whatever we wanted to the CC,
237 including having this work sanely.
239 ===-------------------------------------------------------------------------===
241 Fix Darwin FP-In-Integer Registers ABI
243 Darwin passes doubles in structures in integer registers, which is very very
244 bad. Add something like a BIT_CONVERT to LLVM, then do an i-p transformation
245 that percolates these things out of functions.
247 Check out how horrible this is:
248 http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html
250 This is an extension of "interprocedural CC unmunging" that can't be done with
253 ===-------------------------------------------------------------------------===
260 return b * 3; // ignore the fact that this is always 3.
266 into something not this:
271 rlwinm r2, r2, 29, 31, 31
273 bgt cr0, LBB1_2 ; UnifiedReturnBlock
275 rlwinm r2, r2, 0, 31, 31
278 LBB1_2: ; UnifiedReturnBlock
282 In particular, the two compares (marked 1) could be shared by reversing one.
283 This could be done in the dag combiner, by swapping a BR_CC when a SETCC of the
284 same operands (but backwards) exists. In this case, this wouldn't save us
285 anything though, because the compares still wouldn't be shared.
287 ===-------------------------------------------------------------------------===
289 We should custom expand setcc instead of pretending that we have it. That
290 would allow us to expose the access of the crbit after the mfcr, allowing
291 that access to be trivially folded into other ops. A simple example:
293 int foo(int a, int b) { return (a < b) << 4; }
300 rlwinm r2, r2, 29, 31, 31
304 ===-------------------------------------------------------------------------===
306 Fold add and sub with constant into non-extern, non-weak addresses so this:
309 void bar(int b) { a = b; }
310 void foo(unsigned char *c) {
327 lbz r2, lo16(_a+3)(r2)
331 ===-------------------------------------------------------------------------===
333 We generate really bad code for this:
335 int f(signed char *a, _Bool b, _Bool c) {
341 ===-------------------------------------------------------------------------===
344 int test(unsigned *P) { return *P >> 24; }
359 ===-------------------------------------------------------------------------===
361 On the G5, logical CR operations are more expensive in their three
362 address form: ops that read/write the same register are half as expensive as
363 those that read from two registers that are different from their destination.
365 We should model this with two separate instructions. The isel should generate
366 the "two address" form of the instructions. When the register allocator
367 detects that it needs to insert a copy due to the two-addresness of the CR
368 logical op, it will invoke PPCInstrInfo::convertToThreeAddress. At this point
369 we can convert to the "three address" instruction, to save code space.
371 This only matters when we start generating cr logical ops.
373 ===-------------------------------------------------------------------------===
375 We should compile these two functions to the same thing:
378 void f(int a, int b, int *P) {
379 *P = (a-b)>=0?(a-b):(b-a);
381 void g(int a, int b, int *P) {
385 Further, they should compile to something better than:
391 bgt cr0, LBB2_2 ; entry
408 ... which is much nicer.
410 This theoretically may help improve twolf slightly (used in dimbox.c:142?).
412 ===-------------------------------------------------------------------------===
414 int foo(int N, int ***W, int **TK, int X) {
417 for (t = 0; t < N; ++t)
418 for (i = 0; i < 4; ++i)
419 W[t / X][i][t % X] = TK[i][t];
424 We generate relatively atrocious code for this loop compared to gcc.
426 We could also strength reduce the rem and the div:
427 http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf
429 ===-------------------------------------------------------------------------===
431 float foo(float X) { return (int)(X); }
446 We could use a target dag combine to turn the lwz/extsw into an lwa when the
447 lwz has a single use. Since LWA is cracked anyway, this would be a codesize
450 ===-------------------------------------------------------------------------===
452 We generate ugly code for this:
454 void func(unsigned int *ret, float dx, float dy, float dz, float dw) {
456 if(dx < -dw) code |= 1;
457 if(dx > dw) code |= 2;
458 if(dy < -dw) code |= 4;
459 if(dy > dw) code |= 8;
460 if(dz < -dw) code |= 16;
461 if(dz > dw) code |= 32;
465 ===-------------------------------------------------------------------------===
467 Complete the signed i32 to FP conversion code using 64-bit registers
468 transformation, good for PI. See PPCISelLowering.cpp, this comment:
470 // FIXME: disable this lowered code. This generates 64-bit register values,
471 // and we don't model the fact that the top part is clobbered by calls. We
472 // need to flag these together so that the value isn't live across a call.
473 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
475 Also, if the registers are spilled to the stack, we have to ensure that all
476 64-bits of them are save/restored, otherwise we will miscompile the code. It
477 sounds like we need to get the 64-bit register classes going.
479 ===-------------------------------------------------------------------------===
481 %struct.B = type { i8, [3 x i8] }
483 define void @bar(%struct.B* %b) {
485 %tmp = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
486 %tmp = load i32* %tmp ; <uint> [#uses=1]
487 %tmp3 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
488 %tmp4 = load i32* %tmp3 ; <uint> [#uses=1]
489 %tmp8 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=2]
490 %tmp9 = load i32* %tmp8 ; <uint> [#uses=1]
491 %tmp4.mask17 = shl i32 %tmp4, i8 1 ; <uint> [#uses=1]
492 %tmp1415 = and i32 %tmp4.mask17, 2147483648 ; <uint> [#uses=1]
493 %tmp.masked = and i32 %tmp, 2147483648 ; <uint> [#uses=1]
494 %tmp11 = or i32 %tmp1415, %tmp.masked ; <uint> [#uses=1]
495 %tmp12 = and i32 %tmp9, 2147483647 ; <uint> [#uses=1]
496 %tmp13 = or i32 %tmp12, %tmp11 ; <uint> [#uses=1]
497 store i32 %tmp13, i32* %tmp8
507 rlwimi r2, r4, 0, 0, 0
511 We could collapse a bunch of those ORs and ANDs and generate the following
516 rlwinm r4, r2, 1, 0, 0
521 ===-------------------------------------------------------------------------===
525 unsigned test6(unsigned x) {
526 return ((x & 0x00FF0000) >> 16) | ((x & 0x000000FF) << 16);
533 rlwinm r3, r3, 16, 0, 31
542 rlwinm r3,r3,16,24,31
547 ===-------------------------------------------------------------------------===
549 Consider a function like this:
551 float foo(float X) { return X + 1234.4123f; }
553 The FP constant ends up in the constant pool, so we need to get the LR register.
554 This ends up producing code like this:
563 addis r2, r2, ha16(.CPI_foo_0-"L00000$pb")
564 lfs f0, lo16(.CPI_foo_0-"L00000$pb")(r2)
570 This is functional, but there is no reason to spill the LR register all the way
571 to the stack (the two marked instrs): spilling it to a GPR is quite enough.
573 Implementing this will require some codegen improvements. Nate writes:
575 "So basically what we need to support the "no stack frame save and restore" is a
576 generalization of the LR optimization to "callee-save regs".
578 Currently, we have LR marked as a callee-save reg. The register allocator sees
579 that it's callee save, and spills it directly to the stack.
581 Ideally, something like this would happen:
583 LR would be in a separate register class from the GPRs. The class of LR would be
584 marked "unspillable". When the register allocator came across an unspillable
585 reg, it would ask "what is the best class to copy this into that I *can* spill"
586 If it gets a class back, which it will in this case (the gprs), it grabs a free
587 register of that class. If it is then later necessary to spill that reg, so be
590 ===-------------------------------------------------------------------------===
594 return X ? 524288 : 0;
602 beq cr0, LBB1_2 ;entry
615 This sort of thing occurs a lot due to globalopt.
617 ===-------------------------------------------------------------------------===
619 We currently compile 32-bit bswap:
621 declare i32 @llvm.bswap.i32(i32 %A)
622 define i32 @test(i32 %A) {
623 %B = call i32 @llvm.bswap.i32(i32 %A)
630 rlwinm r2, r3, 24, 16, 23
632 rlwimi r2, r3, 8, 24, 31
633 rlwimi r4, r3, 8, 8, 15
634 rlwimi r4, r2, 0, 16, 31
638 it would be more efficient to produce:
641 rlwinm r3,r3,8,0xffffffff
643 rlwimi r3,r0,24,16,23
646 ===-------------------------------------------------------------------------===
648 test/CodeGen/PowerPC/2007-03-24-cntlzd.ll compiles to:
650 __ZNK4llvm5APInt17countLeadingZerosEv:
653 or r2, r2, r2 <<-- silly.
657 The dead or is a 'truncate' from 64- to 32-bits.
659 ===-------------------------------------------------------------------------===
661 We generate horrible ppc code for this:
673 addi r5, r5, 1 ;; Extra IV for the exit value compare.
677 xoris r6, r5, 30 ;; This is due to a large immediate.
678 cmplwi cr0, r6, 33920
681 //===---------------------------------------------------------------------===//
685 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
686 { return std::make_pair(a + b, a + b < a); }
687 bool no_overflow(unsigned a, unsigned b)
688 { return !full_add(a, b).second; }
705 rlwinm r2, r2, 29, 31, 31
709 //===---------------------------------------------------------------------===//
711 We compile some FP comparisons into an mfcr with two rlwinms and an or. For
714 int test(double x, double y) { return islessequal(x, y);}
715 int test2(double x, double y) { return islessgreater(x, y);}
716 int test3(double x, double y) { return !islessequal(x, y);}
718 Compiles into (all three are similar, but the bits differ):
723 rlwinm r3, r2, 29, 31, 31
724 rlwinm r2, r2, 31, 31, 31
728 GCC compiles this into:
737 which is more efficient and can use mfocr. See PR642 for some more context.
739 //===---------------------------------------------------------------------===//