1 //===- README.txt - Notes for improving PowerPC-specific code gen ---------===//
5 * implement do-loop -> bdnz transform
7 ===-------------------------------------------------------------------------===
9 Support 'update' load/store instructions. These are cracked on the G5, but are
12 With preinc enabled, this:
14 long *%test4(long *%X, long *%dest) {
15 %Y = getelementptr long* %X, int 4
17 store long %A, long* %dest
32 with -sched=list-burr, I get:
41 ===-------------------------------------------------------------------------===
43 We compile the hottest inner loop of viterbi to:
54 bne cr0, LBB1_83 ;bb420.i
56 The CBE manages to produce:
67 This could be much better (bdnz instead of bdz) but it still beats us. If we
68 produced this with bdnz, the loop would be a single dispatch group.
70 ===-------------------------------------------------------------------------===
87 This is effectively a simple form of predication.
89 ===-------------------------------------------------------------------------===
91 Lump the constant pool for each function into ONE pic object, and reference
92 pieces of it as offsets from the start. For functions like this (contrived
93 to have lots of constants obviously):
95 double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
100 lis r2, ha16(.CPI_X_0)
101 lfd f0, lo16(.CPI_X_0)(r2)
102 lis r2, ha16(.CPI_X_1)
103 lfd f2, lo16(.CPI_X_1)(r2)
105 lis r2, ha16(.CPI_X_2)
106 lfd f1, lo16(.CPI_X_2)(r2)
107 lis r2, ha16(.CPI_X_3)
108 lfd f2, lo16(.CPI_X_3)(r2)
112 It would be better to materialize .CPI_X into a register, then use immediates
113 off of the register to avoid the lis's. This is even more important in PIC
116 Note that this (and the static variable version) is discussed here for GCC:
117 http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
119 Here's another example (the sgn function):
120 double testf(double a) {
121 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
124 it produces a BB like this:
126 lis r2, ha16(LCPI1_0)
127 lfs f0, lo16(LCPI1_0)(r2)
128 lis r2, ha16(LCPI1_1)
129 lis r3, ha16(LCPI1_2)
130 lfs f2, lo16(LCPI1_2)(r3)
131 lfs f3, lo16(LCPI1_1)(r2)
136 ===-------------------------------------------------------------------------===
138 PIC Code Gen IPO optimization:
140 Squish small scalar globals together into a single global struct, allowing the
141 address of the struct to be CSE'd, avoiding PIC accesses (also reduces the size
142 of the GOT on targets with one).
144 Note that this is discussed here for GCC:
145 http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
147 ===-------------------------------------------------------------------------===
149 Implement Newton-Rhapson method for improving estimate instructions to the
150 correct accuracy, and implementing divide as multiply by reciprocal when it has
151 more than one use. Itanium will want this too.
153 ===-------------------------------------------------------------------------===
157 int %f1(int %a, int %b) {
158 %tmp.1 = and int %a, 15 ; <int> [#uses=1]
159 %tmp.3 = and int %b, 240 ; <int> [#uses=1]
160 %tmp.4 = or int %tmp.3, %tmp.1 ; <int> [#uses=1]
164 without a copy. We make this currently:
167 rlwinm r2, r4, 0, 24, 27
168 rlwimi r2, r3, 0, 28, 31
172 The two-addr pass or RA needs to learn when it is profitable to commute an
173 instruction to avoid a copy AFTER the 2-addr instruction. The 2-addr pass
174 currently only commutes to avoid inserting a copy BEFORE the two addr instr.
176 ===-------------------------------------------------------------------------===
178 Compile offsets from allocas:
181 %X = alloca { int, int }
182 %Y = getelementptr {int,int}* %X, int 0, uint 1
186 into a single add, not two:
193 --> important for C++.
195 ===-------------------------------------------------------------------------===
197 No loads or stores of the constants should be needed:
199 struct foo { double X, Y; };
200 void xxx(struct foo F);
201 void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }
203 ===-------------------------------------------------------------------------===
205 Darwin Stub LICM optimization:
211 Have to go through an indirect stub if bar is external or linkonce. It would
212 be better to compile it as:
217 which only computes the address of bar once (instead of each time through the
218 stub). This is Darwin specific and would have to be done in the code generator.
219 Probably not a win on x86.
221 ===-------------------------------------------------------------------------===
223 Simple IPO for argument passing, change:
224 void foo(int X, double Y, int Z) -> void foo(int X, int Z, double Y)
226 the Darwin ABI specifies that any integer arguments in the first 32 bytes worth
227 of arguments get assigned to r3 through r10. That is, if you have a function
228 foo(int, double, int) you get r3, f1, r6, since the 64 bit double ate up the
229 argument bytes for r4 and r5. The trick then would be to shuffle the argument
230 order for functions we can internalize so that the maximum number of
231 integers/pointers get passed in regs before you see any of the fp arguments.
233 Instead of implementing this, it would actually probably be easier to just
234 implement a PPC fastcc, where we could do whatever we wanted to the CC,
235 including having this work sanely.
237 ===-------------------------------------------------------------------------===
239 Fix Darwin FP-In-Integer Registers ABI
241 Darwin passes doubles in structures in integer registers, which is very very
242 bad. Add something like a BIT_CONVERT to LLVM, then do an i-p transformation
243 that percolates these things out of functions.
245 Check out how horrible this is:
246 http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html
248 This is an extension of "interprocedural CC unmunging" that can't be done with
251 ===-------------------------------------------------------------------------===
258 return b * 3; // ignore the fact that this is always 3.
264 into something not this:
269 rlwinm r2, r2, 29, 31, 31
271 bgt cr0, LBB1_2 ; UnifiedReturnBlock
273 rlwinm r2, r2, 0, 31, 31
276 LBB1_2: ; UnifiedReturnBlock
280 In particular, the two compares (marked 1) could be shared by reversing one.
281 This could be done in the dag combiner, by swapping a BR_CC when a SETCC of the
282 same operands (but backwards) exists. In this case, this wouldn't save us
283 anything though, because the compares still wouldn't be shared.
285 ===-------------------------------------------------------------------------===
287 We should custom expand setcc instead of pretending that we have it. That
288 would allow us to expose the access of the crbit after the mfcr, allowing
289 that access to be trivially folded into other ops. A simple example:
291 int foo(int a, int b) { return (a < b) << 4; }
298 rlwinm r2, r2, 29, 31, 31
302 ===-------------------------------------------------------------------------===
304 Fold add and sub with constant into non-extern, non-weak addresses so this:
307 void bar(int b) { a = b; }
308 void foo(unsigned char *c) {
325 lbz r2, lo16(_a+3)(r2)
329 ===-------------------------------------------------------------------------===
331 We generate really bad code for this:
333 int f(signed char *a, _Bool b, _Bool c) {
339 ===-------------------------------------------------------------------------===
342 int test(unsigned *P) { return *P >> 24; }
357 ===-------------------------------------------------------------------------===
359 On the G5, logical CR operations are more expensive in their three
360 address form: ops that read/write the same register are half as expensive as
361 those that read from two registers that are different from their destination.
363 We should model this with two separate instructions. The isel should generate
364 the "two address" form of the instructions. When the register allocator
365 detects that it needs to insert a copy due to the two-addresness of the CR
366 logical op, it will invoke PPCInstrInfo::convertToThreeAddress. At this point
367 we can convert to the "three address" instruction, to save code space.
369 This only matters when we start generating cr logical ops.
371 ===-------------------------------------------------------------------------===
373 We should compile these two functions to the same thing:
376 void f(int a, int b, int *P) {
377 *P = (a-b)>=0?(a-b):(b-a);
379 void g(int a, int b, int *P) {
383 Further, they should compile to something better than:
389 bgt cr0, LBB2_2 ; entry
406 ... which is much nicer.
408 This theoretically may help improve twolf slightly (used in dimbox.c:142?).
410 ===-------------------------------------------------------------------------===
412 int foo(int N, int ***W, int **TK, int X) {
415 for (t = 0; t < N; ++t)
416 for (i = 0; i < 4; ++i)
417 W[t / X][i][t % X] = TK[i][t];
422 We generate relatively atrocious code for this loop compared to gcc.
424 We could also strength reduce the rem and the div:
425 http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf
427 ===-------------------------------------------------------------------------===
429 float foo(float X) { return (int)(X); }
444 We could use a target dag combine to turn the lwz/extsw into an lwa when the
445 lwz has a single use. Since LWA is cracked anyway, this would be a codesize
448 ===-------------------------------------------------------------------------===
450 We generate ugly code for this:
452 void func(unsigned int *ret, float dx, float dy, float dz, float dw) {
454 if(dx < -dw) code |= 1;
455 if(dx > dw) code |= 2;
456 if(dy < -dw) code |= 4;
457 if(dy > dw) code |= 8;
458 if(dz < -dw) code |= 16;
459 if(dz > dw) code |= 32;
463 ===-------------------------------------------------------------------------===
465 Complete the signed i32 to FP conversion code using 64-bit registers
466 transformation, good for PI. See PPCISelLowering.cpp, this comment:
468 // FIXME: disable this lowered code. This generates 64-bit register values,
469 // and we don't model the fact that the top part is clobbered by calls. We
470 // need to flag these together so that the value isn't live across a call.
471 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
473 Also, if the registers are spilled to the stack, we have to ensure that all
474 64-bits of them are save/restored, otherwise we will miscompile the code. It
475 sounds like we need to get the 64-bit register classes going.
477 ===-------------------------------------------------------------------------===
479 %struct.B = type { i8, [3 x i8] }
481 define void @bar(%struct.B* %b) {
483 %tmp = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
484 %tmp = load i32* %tmp ; <uint> [#uses=1]
485 %tmp3 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
486 %tmp4 = load i32* %tmp3 ; <uint> [#uses=1]
487 %tmp8 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=2]
488 %tmp9 = load i32* %tmp8 ; <uint> [#uses=1]
489 %tmp4.mask17 = shl i32 %tmp4, i8 1 ; <uint> [#uses=1]
490 %tmp1415 = and i32 %tmp4.mask17, 2147483648 ; <uint> [#uses=1]
491 %tmp.masked = and i32 %tmp, 2147483648 ; <uint> [#uses=1]
492 %tmp11 = or i32 %tmp1415, %tmp.masked ; <uint> [#uses=1]
493 %tmp12 = and i32 %tmp9, 2147483647 ; <uint> [#uses=1]
494 %tmp13 = or i32 %tmp12, %tmp11 ; <uint> [#uses=1]
495 store i32 %tmp13, i32* %tmp8
505 rlwimi r2, r4, 0, 0, 0
509 We could collapse a bunch of those ORs and ANDs and generate the following
514 rlwinm r4, r2, 1, 0, 0
519 ===-------------------------------------------------------------------------===
523 unsigned test6(unsigned x) {
524 return ((x & 0x00FF0000) >> 16) | ((x & 0x000000FF) << 16);
531 rlwinm r3, r3, 16, 0, 31
540 rlwinm r3,r3,16,24,31
545 ===-------------------------------------------------------------------------===
547 Consider a function like this:
549 float foo(float X) { return X + 1234.4123f; }
551 The FP constant ends up in the constant pool, so we need to get the LR register.
552 This ends up producing code like this:
561 addis r2, r2, ha16(.CPI_foo_0-"L00000$pb")
562 lfs f0, lo16(.CPI_foo_0-"L00000$pb")(r2)
568 This is functional, but there is no reason to spill the LR register all the way
569 to the stack (the two marked instrs): spilling it to a GPR is quite enough.
571 Implementing this will require some codegen improvements. Nate writes:
573 "So basically what we need to support the "no stack frame save and restore" is a
574 generalization of the LR optimization to "callee-save regs".
576 Currently, we have LR marked as a callee-save reg. The register allocator sees
577 that it's callee save, and spills it directly to the stack.
579 Ideally, something like this would happen:
581 LR would be in a separate register class from the GPRs. The class of LR would be
582 marked "unspillable". When the register allocator came across an unspillable
583 reg, it would ask "what is the best class to copy this into that I *can* spill"
584 If it gets a class back, which it will in this case (the gprs), it grabs a free
585 register of that class. If it is then later necessary to spill that reg, so be
588 ===-------------------------------------------------------------------------===
592 return X ? 524288 : 0;
600 beq cr0, LBB1_2 ;entry
613 This sort of thing occurs a lot due to globalopt.
615 ===-------------------------------------------------------------------------===
617 We currently compile 32-bit bswap:
619 declare i32 @llvm.bswap.i32(i32 %A)
620 define i32 @test(i32 %A) {
621 %B = call i32 @llvm.bswap.i32(i32 %A)
628 rlwinm r2, r3, 24, 16, 23
630 rlwimi r2, r3, 8, 24, 31
631 rlwimi r4, r3, 8, 8, 15
632 rlwimi r4, r2, 0, 16, 31
636 it would be more efficient to produce:
639 rlwinm r3,r3,8,0xffffffff
641 rlwimi r3,r0,24,16,23
644 ===-------------------------------------------------------------------------===
646 test/CodeGen/PowerPC/2007-03-24-cntlzd.ll compiles to:
648 __ZNK4llvm5APInt17countLeadingZerosEv:
651 or r2, r2, r2 <<-- silly.
655 The dead or is a 'truncate' from 64- to 32-bits.
657 ===-------------------------------------------------------------------------===
659 We generate horrible ppc code for this:
671 addi r5, r5, 1 ;; Extra IV for the exit value compare.
675 xoris r6, r5, 30 ;; This is due to a large immediate.
676 cmplwi cr0, r6, 33920
679 //===---------------------------------------------------------------------===//
683 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
684 { return std::make_pair(a + b, a + b < a); }
685 bool no_overflow(unsigned a, unsigned b)
686 { return !full_add(a, b).second; }
703 rlwinm r2, r2, 29, 31, 31
707 //===---------------------------------------------------------------------===//