1 //===- README.txt - Notes for improving PowerPC-specific code gen ---------===//
5 * lmw/stmw pass a la arm load store optimizer for prolog/epilog
7 ===-------------------------------------------------------------------------===
11 long f2 (long x) { return 0xfffffff000000000UL; }
12 long f3 (long x) { return 0x1ffffffffUL; }
39 ===-------------------------------------------------------------------------===
43 unsigned add32carry(unsigned sum, unsigned x) {
50 Should compile to something like:
60 rlwinm r4, r4, 29, 31, 31
65 ===-------------------------------------------------------------------------===
67 Support 'update' load/store instructions. These are cracked on the G5, but are
70 With preinc enabled, this:
72 long *%test4(long *%X, long *%dest) {
73 %Y = getelementptr long* %X, int 4
75 store long %A, long* %dest
90 with -sched=list-burr, I get:
99 ===-------------------------------------------------------------------------===
101 We compile the hottest inner loop of viterbi to:
112 bne cr0, LBB1_83 ;bb420.i
114 The CBE manages to produce:
125 This could be much better (bdnz instead of bdz) but it still beats us. If we
126 produced this with bdnz, the loop would be a single dispatch group.
128 ===-------------------------------------------------------------------------===
145 This is effectively a simple form of predication.
147 ===-------------------------------------------------------------------------===
149 Lump the constant pool for each function into ONE pic object, and reference
150 pieces of it as offsets from the start. For functions like this (contrived
151 to have lots of constants obviously):
153 double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
158 lis r2, ha16(.CPI_X_0)
159 lfd f0, lo16(.CPI_X_0)(r2)
160 lis r2, ha16(.CPI_X_1)
161 lfd f2, lo16(.CPI_X_1)(r2)
163 lis r2, ha16(.CPI_X_2)
164 lfd f1, lo16(.CPI_X_2)(r2)
165 lis r2, ha16(.CPI_X_3)
166 lfd f2, lo16(.CPI_X_3)(r2)
170 It would be better to materialize .CPI_X into a register, then use immediates
171 off of the register to avoid the lis's. This is even more important in PIC
174 Note that this (and the static variable version) is discussed here for GCC:
175 http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
177 Here's another example (the sgn function):
178 double testf(double a) {
179 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
182 it produces a BB like this:
184 lis r2, ha16(LCPI1_0)
185 lfs f0, lo16(LCPI1_0)(r2)
186 lis r2, ha16(LCPI1_1)
187 lis r3, ha16(LCPI1_2)
188 lfs f2, lo16(LCPI1_2)(r3)
189 lfs f3, lo16(LCPI1_1)(r2)
194 ===-------------------------------------------------------------------------===
196 PIC Code Gen IPO optimization:
198 Squish small scalar globals together into a single global struct, allowing the
199 address of the struct to be CSE'd, avoiding PIC accesses (also reduces the size
200 of the GOT on targets with one).
202 Note that this is discussed here for GCC:
203 http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
205 ===-------------------------------------------------------------------------===
207 Implement Newton-Rhapson method for improving estimate instructions to the
208 correct accuracy, and implementing divide as multiply by reciprocal when it has
209 more than one use. Itanium would want this too.
211 ===-------------------------------------------------------------------------===
213 Compile offsets from allocas:
216 %X = alloca { int, int }
217 %Y = getelementptr {int,int}* %X, int 0, uint 1
221 into a single add, not two:
228 --> important for C++.
230 ===-------------------------------------------------------------------------===
232 No loads or stores of the constants should be needed:
234 struct foo { double X, Y; };
235 void xxx(struct foo F);
236 void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }
238 ===-------------------------------------------------------------------------===
242 We still generate calls to foo$stub, and stubs, on Darwin. This is not
243 necessary when building with the Leopard (10.5) or later linker, as stubs are
244 generated by ld when necessary. Parameterizing this based on the deployment
245 target (-mmacosx-version-min) is probably enough. x86-32 does this right, see
248 ===-------------------------------------------------------------------------===
250 Darwin Stub LICM optimization:
256 Have to go through an indirect stub if bar is external or linkonce. It would
257 be better to compile it as:
262 which only computes the address of bar once (instead of each time through the
263 stub). This is Darwin specific and would have to be done in the code generator.
264 Probably not a win on x86.
266 ===-------------------------------------------------------------------------===
268 Simple IPO for argument passing, change:
269 void foo(int X, double Y, int Z) -> void foo(int X, int Z, double Y)
271 the Darwin ABI specifies that any integer arguments in the first 32 bytes worth
272 of arguments get assigned to r3 through r10. That is, if you have a function
273 foo(int, double, int) you get r3, f1, r6, since the 64 bit double ate up the
274 argument bytes for r4 and r5. The trick then would be to shuffle the argument
275 order for functions we can internalize so that the maximum number of
276 integers/pointers get passed in regs before you see any of the fp arguments.
278 Instead of implementing this, it would actually probably be easier to just
279 implement a PPC fastcc, where we could do whatever we wanted to the CC,
280 including having this work sanely.
282 ===-------------------------------------------------------------------------===
284 Fix Darwin FP-In-Integer Registers ABI
286 Darwin passes doubles in structures in integer registers, which is very very
287 bad. Add something like a BITCAST to LLVM, then do an i-p transformation that
288 percolates these things out of functions.
290 Check out how horrible this is:
291 http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html
293 This is an extension of "interprocedural CC unmunging" that can't be done with
296 ===-------------------------------------------------------------------------===
303 return b * 3; // ignore the fact that this is always 3.
309 into something not this:
314 rlwinm r2, r2, 29, 31, 31
316 bgt cr0, LBB1_2 ; UnifiedReturnBlock
318 rlwinm r2, r2, 0, 31, 31
321 LBB1_2: ; UnifiedReturnBlock
325 In particular, the two compares (marked 1) could be shared by reversing one.
326 This could be done in the dag combiner, by swapping a BR_CC when a SETCC of the
327 same operands (but backwards) exists. In this case, this wouldn't save us
328 anything though, because the compares still wouldn't be shared.
330 ===-------------------------------------------------------------------------===
332 We should custom expand setcc instead of pretending that we have it. That
333 would allow us to expose the access of the crbit after the mfcr, allowing
334 that access to be trivially folded into other ops. A simple example:
336 int foo(int a, int b) { return (a < b) << 4; }
343 rlwinm r2, r2, 29, 31, 31
347 ===-------------------------------------------------------------------------===
349 Fold add and sub with constant into non-extern, non-weak addresses so this:
352 void bar(int b) { a = b; }
353 void foo(unsigned char *c) {
370 lbz r2, lo16(_a+3)(r2)
374 ===-------------------------------------------------------------------------===
376 We generate really bad code for this:
378 int f(signed char *a, _Bool b, _Bool c) {
384 ===-------------------------------------------------------------------------===
387 int test(unsigned *P) { return *P >> 24; }
402 ===-------------------------------------------------------------------------===
404 On the G5, logical CR operations are more expensive in their three
405 address form: ops that read/write the same register are half as expensive as
406 those that read from two registers that are different from their destination.
408 We should model this with two separate instructions. The isel should generate
409 the "two address" form of the instructions. When the register allocator
410 detects that it needs to insert a copy due to the two-addresness of the CR
411 logical op, it will invoke PPCInstrInfo::convertToThreeAddress. At this point
412 we can convert to the "three address" instruction, to save code space.
414 This only matters when we start generating cr logical ops.
416 ===-------------------------------------------------------------------------===
418 We should compile these two functions to the same thing:
421 void f(int a, int b, int *P) {
422 *P = (a-b)>=0?(a-b):(b-a);
424 void g(int a, int b, int *P) {
428 Further, they should compile to something better than:
434 bgt cr0, LBB2_2 ; entry
451 ... which is much nicer.
453 This theoretically may help improve twolf slightly (used in dimbox.c:142?).
455 ===-------------------------------------------------------------------------===
458 define i32 @clamp0g(i32 %a) {
460 %cmp = icmp slt i32 %a, 0
461 %sel = select i1 %cmp, i32 0, i32 %a
465 Is compile to this with the PowerPC (32-bit) backend:
477 This could be reduced to the much simpler:
484 ===-------------------------------------------------------------------------===
486 int foo(int N, int ***W, int **TK, int X) {
489 for (t = 0; t < N; ++t)
490 for (i = 0; i < 4; ++i)
491 W[t / X][i][t % X] = TK[i][t];
496 We generate relatively atrocious code for this loop compared to gcc.
498 We could also strength reduce the rem and the div:
499 http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf
501 ===-------------------------------------------------------------------------===
503 float foo(float X) { return (int)(X); }
518 We could use a target dag combine to turn the lwz/extsw into an lwa when the
519 lwz has a single use. Since LWA is cracked anyway, this would be a codesize
522 ===-------------------------------------------------------------------------===
524 We generate ugly code for this:
526 void func(unsigned int *ret, float dx, float dy, float dz, float dw) {
528 if(dx < -dw) code |= 1;
529 if(dx > dw) code |= 2;
530 if(dy < -dw) code |= 4;
531 if(dy > dw) code |= 8;
532 if(dz < -dw) code |= 16;
533 if(dz > dw) code |= 32;
537 ===-------------------------------------------------------------------------===
539 Complete the signed i32 to FP conversion code using 64-bit registers
540 transformation, good for PI. See PPCISelLowering.cpp, this comment:
542 // FIXME: disable this lowered code. This generates 64-bit register values,
543 // and we don't model the fact that the top part is clobbered by calls. We
544 // need to flag these together so that the value isn't live across a call.
545 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
547 Also, if the registers are spilled to the stack, we have to ensure that all
548 64-bits of them are save/restored, otherwise we will miscompile the code. It
549 sounds like we need to get the 64-bit register classes going.
551 ===-------------------------------------------------------------------------===
553 %struct.B = type { i8, [3 x i8] }
555 define void @bar(%struct.B* %b) {
557 %tmp = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
558 %tmp = load i32* %tmp ; <uint> [#uses=1]
559 %tmp3 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
560 %tmp4 = load i32* %tmp3 ; <uint> [#uses=1]
561 %tmp8 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=2]
562 %tmp9 = load i32* %tmp8 ; <uint> [#uses=1]
563 %tmp4.mask17 = shl i32 %tmp4, i8 1 ; <uint> [#uses=1]
564 %tmp1415 = and i32 %tmp4.mask17, 2147483648 ; <uint> [#uses=1]
565 %tmp.masked = and i32 %tmp, 2147483648 ; <uint> [#uses=1]
566 %tmp11 = or i32 %tmp1415, %tmp.masked ; <uint> [#uses=1]
567 %tmp12 = and i32 %tmp9, 2147483647 ; <uint> [#uses=1]
568 %tmp13 = or i32 %tmp12, %tmp11 ; <uint> [#uses=1]
569 store i32 %tmp13, i32* %tmp8
579 rlwimi r2, r4, 0, 0, 0
583 We could collapse a bunch of those ORs and ANDs and generate the following
588 rlwinm r4, r2, 1, 0, 0
593 ===-------------------------------------------------------------------------===
597 unsigned test6(unsigned x) {
598 return ((x & 0x00FF0000) >> 16) | ((x & 0x000000FF) << 16);
605 rlwinm r3, r3, 16, 0, 31
614 rlwinm r3,r3,16,24,31
619 ===-------------------------------------------------------------------------===
621 Consider a function like this:
623 float foo(float X) { return X + 1234.4123f; }
625 The FP constant ends up in the constant pool, so we need to get the LR register.
626 This ends up producing code like this:
635 addis r2, r2, ha16(.CPI_foo_0-"L00000$pb")
636 lfs f0, lo16(.CPI_foo_0-"L00000$pb")(r2)
642 This is functional, but there is no reason to spill the LR register all the way
643 to the stack (the two marked instrs): spilling it to a GPR is quite enough.
645 Implementing this will require some codegen improvements. Nate writes:
647 "So basically what we need to support the "no stack frame save and restore" is a
648 generalization of the LR optimization to "callee-save regs".
650 Currently, we have LR marked as a callee-save reg. The register allocator sees
651 that it's callee save, and spills it directly to the stack.
653 Ideally, something like this would happen:
655 LR would be in a separate register class from the GPRs. The class of LR would be
656 marked "unspillable". When the register allocator came across an unspillable
657 reg, it would ask "what is the best class to copy this into that I *can* spill"
658 If it gets a class back, which it will in this case (the gprs), it grabs a free
659 register of that class. If it is then later necessary to spill that reg, so be
662 ===-------------------------------------------------------------------------===
666 return X ? 524288 : 0;
674 beq cr0, LBB1_2 ;entry
687 This sort of thing occurs a lot due to globalopt.
689 ===-------------------------------------------------------------------------===
693 define i32 @bar(i32 %x) nounwind readnone ssp {
695 %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1]
696 %neg = sext i1 %0 to i32 ; <i32> [#uses=1]
708 it would be better to produce:
715 ===-------------------------------------------------------------------------===
717 We currently compile 32-bit bswap:
719 declare i32 @llvm.bswap.i32(i32 %A)
720 define i32 @test(i32 %A) {
721 %B = call i32 @llvm.bswap.i32(i32 %A)
728 rlwinm r2, r3, 24, 16, 23
730 rlwimi r2, r3, 8, 24, 31
731 rlwimi r4, r3, 8, 8, 15
732 rlwimi r4, r2, 0, 16, 31
736 it would be more efficient to produce:
739 rlwinm r3,r3,8,0xffffffff
741 rlwimi r3,r0,24,16,23
744 ===-------------------------------------------------------------------------===
746 test/CodeGen/PowerPC/2007-03-24-cntlzd.ll compiles to:
748 __ZNK4llvm5APInt17countLeadingZerosEv:
751 or r2, r2, r2 <<-- silly.
755 The dead or is a 'truncate' from 64- to 32-bits.
757 ===-------------------------------------------------------------------------===
759 We generate horrible ppc code for this:
771 addi r5, r5, 1 ;; Extra IV for the exit value compare.
775 xoris r6, r5, 30 ;; This is due to a large immediate.
776 cmplwi cr0, r6, 33920
779 //===---------------------------------------------------------------------===//
783 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
784 { return std::make_pair(a + b, a + b < a); }
785 bool no_overflow(unsigned a, unsigned b)
786 { return !full_add(a, b).second; }
803 rlwinm r2, r2, 29, 31, 31
807 //===---------------------------------------------------------------------===//
809 We compile some FP comparisons into an mfcr with two rlwinms and an or. For
812 int test(double x, double y) { return islessequal(x, y);}
813 int test2(double x, double y) { return islessgreater(x, y);}
814 int test3(double x, double y) { return !islessequal(x, y);}
816 Compiles into (all three are similar, but the bits differ):
821 rlwinm r3, r2, 29, 31, 31
822 rlwinm r2, r2, 31, 31, 31
826 GCC compiles this into:
835 which is more efficient and can use mfocr. See PR642 for some more context.
837 //===---------------------------------------------------------------------===//
839 void foo(float *data, float d) {
841 for (i = 0; i < 8000; i++)
844 void foo2(float *data, float d) {
847 for (i = 0; i < 8000; i++) {
860 cmplwi cr0, r4, 32000
869 cmplwi cr0, r4, 32000
874 The 'mr' could be eliminated to folding the add into the cmp better.
876 //===---------------------------------------------------------------------===//
877 Codegen for the following (low-probability) case deteriorated considerably
878 when the correctness fixes for unordered comparisons went in (PR 642, 58871).
879 It should be possible to recover the code quality described in the comments.
881 ; RUN: llvm-as < %s | llc -march=ppc32 | grep or | count 3
882 ; This should produce one 'or' or 'cror' instruction per function.
884 ; RUN: llvm-as < %s | llc -march=ppc32 | grep mfcr | count 3
887 define i32 @test(double %x, double %y) nounwind {
889 %tmp3 = fcmp ole double %x, %y ; <i1> [#uses=1]
890 %tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
894 define i32 @test2(double %x, double %y) nounwind {
896 %tmp3 = fcmp one double %x, %y ; <i1> [#uses=1]
897 %tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
901 define i32 @test3(double %x, double %y) nounwind {
903 %tmp3 = fcmp ugt double %x, %y ; <i1> [#uses=1]
904 %tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
907 //===----------------------------------------------------------------------===//
908 ; RUN: llvm-as < %s | llc -march=ppc32 | not grep fneg
910 ; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and
911 ; should not be generated except with -enable-finite-only-fp-math or the like).
912 ; With the correctness fixes for PR642 (58871) LowerSELECT_CC would need to
913 ; recognize a more elaborate tree than a simple SETxx.
915 define double @test_FNEG_sel(double %A, double %B, double %C) {
916 %D = fsub double -0.000000e+00, %A ; <double> [#uses=1]
917 %Cond = fcmp ugt double %D, -0.000000e+00 ; <i1> [#uses=1]
918 %E = select i1 %Cond, double %B, double %C ; <double> [#uses=1]
922 //===----------------------------------------------------------------------===//
923 The save/restore sequence for CR in prolog/epilog is terrible:
924 - Each CR subreg is saved individually, rather than doing one save as a unit.
925 - On Darwin, the save is done after the decrement of SP, which means the offset
926 from SP of the save slot can be too big for a store instruction, which means we
927 need an additional register (currently hacked in 96015+96020; the solution there
928 is correct, but poor).
929 - On SVR4 the same thing can happen, and I don't think saving before the SP
930 decrement is safe on that target, as there is no red zone. This is currently
931 broken AFAIK, although it's not a target I can exercise.
932 The following demonstrates the problem:
933 extern void bar(char *p);
937 __asm__("" ::: "cr2");