1 //===- README.txt - Notes for improving PowerPC-specific code gen ---------===//
4 * lmw/stmw pass a la arm load store optimizer for prolog/epilog
6 ===-------------------------------------------------------------------------===
10 unsigned add32carry(unsigned sum, unsigned x) {
17 Should compile to something like:
27 rlwinm r4, r4, 29, 31, 31
32 ===-------------------------------------------------------------------------===
34 We compile the hottest inner loop of viterbi to:
45 bne cr0, LBB1_83 ;bb420.i
47 The CBE manages to produce:
58 This could be much better (bdnz instead of bdz) but it still beats us. If we
59 produced this with bdnz, the loop would be a single dispatch group.
61 ===-------------------------------------------------------------------------===
63 Lump the constant pool for each function into ONE pic object, and reference
64 pieces of it as offsets from the start. For functions like this (contrived
65 to have lots of constants obviously):
67 double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
72 lis r2, ha16(.CPI_X_0)
73 lfd f0, lo16(.CPI_X_0)(r2)
74 lis r2, ha16(.CPI_X_1)
75 lfd f2, lo16(.CPI_X_1)(r2)
77 lis r2, ha16(.CPI_X_2)
78 lfd f1, lo16(.CPI_X_2)(r2)
79 lis r2, ha16(.CPI_X_3)
80 lfd f2, lo16(.CPI_X_3)(r2)
84 It would be better to materialize .CPI_X into a register, then use immediates
85 off of the register to avoid the lis's. This is even more important in PIC
88 Note that this (and the static variable version) is discussed here for GCC:
89 http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
91 Here's another example (the sgn function):
92 double testf(double a) {
93 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
96 it produces a BB like this:
99 lfs f0, lo16(LCPI1_0)(r2)
100 lis r2, ha16(LCPI1_1)
101 lis r3, ha16(LCPI1_2)
102 lfs f2, lo16(LCPI1_2)(r3)
103 lfs f3, lo16(LCPI1_1)(r2)
108 ===-------------------------------------------------------------------------===
110 PIC Code Gen IPO optimization:
112 Squish small scalar globals together into a single global struct, allowing the
113 address of the struct to be CSE'd, avoiding PIC accesses (also reduces the size
114 of the GOT on targets with one).
116 Note that this is discussed here for GCC:
117 http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
119 ===-------------------------------------------------------------------------===
121 No loads or stores of the constants should be needed:
123 struct foo { double X, Y; };
124 void xxx(struct foo F);
125 void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }
127 ===-------------------------------------------------------------------------===
131 We still generate calls to foo$stub, and stubs, on Darwin. This is not
132 necessary when building with the Leopard (10.5) or later linker, as stubs are
133 generated by ld when necessary. Parameterizing this based on the deployment
134 target (-mmacosx-version-min) is probably enough. x86-32 does this right, see
137 ===-------------------------------------------------------------------------===
139 Darwin Stub LICM optimization:
145 Have to go through an indirect stub if bar is external or linkonce. It would
146 be better to compile it as:
151 which only computes the address of bar once (instead of each time through the
152 stub). This is Darwin specific and would have to be done in the code generator.
153 Probably not a win on x86.
155 ===-------------------------------------------------------------------------===
157 Simple IPO for argument passing, change:
158 void foo(int X, double Y, int Z) -> void foo(int X, int Z, double Y)
160 the Darwin ABI specifies that any integer arguments in the first 32 bytes worth
161 of arguments get assigned to r3 through r10. That is, if you have a function
162 foo(int, double, int) you get r3, f1, r6, since the 64 bit double ate up the
163 argument bytes for r4 and r5. The trick then would be to shuffle the argument
164 order for functions we can internalize so that the maximum number of
165 integers/pointers get passed in regs before you see any of the fp arguments.
167 Instead of implementing this, it would actually probably be easier to just
168 implement a PPC fastcc, where we could do whatever we wanted to the CC,
169 including having this work sanely.
171 ===-------------------------------------------------------------------------===
173 Fix Darwin FP-In-Integer Registers ABI
175 Darwin passes doubles in structures in integer registers, which is very very
176 bad. Add something like a BITCAST to LLVM, then do an i-p transformation that
177 percolates these things out of functions.
179 Check out how horrible this is:
180 http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html
182 This is an extension of "interprocedural CC unmunging" that can't be done with
185 ===-------------------------------------------------------------------------===
187 Fold add and sub with constant into non-extern, non-weak addresses so this:
190 void bar(int b) { a = b; }
191 void foo(unsigned char *c) {
208 lbz r2, lo16(_a+3)(r2)
212 ===-------------------------------------------------------------------------===
214 We generate really bad code for this:
216 int f(signed char *a, _Bool b, _Bool c) {
222 ===-------------------------------------------------------------------------===
224 On the G5, logical CR operations are more expensive in their three
225 address form: ops that read/write the same register are half as expensive as
226 those that read from two registers that are different from their destination.
228 We should model this with two separate instructions. The isel should generate
229 the "two address" form of the instructions. When the register allocator
230 detects that it needs to insert a copy due to the two-addresness of the CR
231 logical op, it will invoke PPCInstrInfo::convertToThreeAddress. At this point
232 we can convert to the "three address" instruction, to save code space.
234 This only matters when we start generating cr logical ops.
236 ===-------------------------------------------------------------------------===
238 We should compile these two functions to the same thing:
241 void f(int a, int b, int *P) {
242 *P = (a-b)>=0?(a-b):(b-a);
244 void g(int a, int b, int *P) {
248 Further, they should compile to something better than:
254 bgt cr0, LBB2_2 ; entry
271 ... which is much nicer.
273 This theoretically may help improve twolf slightly (used in dimbox.c:142?).
275 ===-------------------------------------------------------------------------===
278 define i32 @clamp0g(i32 %a) {
280 %cmp = icmp slt i32 %a, 0
281 %sel = select i1 %cmp, i32 0, i32 %a
285 Is compile to this with the PowerPC (32-bit) backend:
297 This could be reduced to the much simpler:
304 ===-------------------------------------------------------------------------===
306 int foo(int N, int ***W, int **TK, int X) {
309 for (t = 0; t < N; ++t)
310 for (i = 0; i < 4; ++i)
311 W[t / X][i][t % X] = TK[i][t];
316 We generate relatively atrocious code for this loop compared to gcc.
318 We could also strength reduce the rem and the div:
319 http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf
321 ===-------------------------------------------------------------------------===
323 float foo(float X) { return (int)(X); }
338 We could use a target dag combine to turn the lwz/extsw into an lwa when the
339 lwz has a single use. Since LWA is cracked anyway, this would be a codesize
342 ===-------------------------------------------------------------------------===
344 We generate ugly code for this:
346 void func(unsigned int *ret, float dx, float dy, float dz, float dw) {
348 if(dx < -dw) code |= 1;
349 if(dx > dw) code |= 2;
350 if(dy < -dw) code |= 4;
351 if(dy > dw) code |= 8;
352 if(dz < -dw) code |= 16;
353 if(dz > dw) code |= 32;
357 ===-------------------------------------------------------------------------===
359 %struct.B = type { i8, [3 x i8] }
361 define void @bar(%struct.B* %b) {
363 %tmp = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
364 %tmp = load i32* %tmp ; <uint> [#uses=1]
365 %tmp3 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
366 %tmp4 = load i32* %tmp3 ; <uint> [#uses=1]
367 %tmp8 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=2]
368 %tmp9 = load i32* %tmp8 ; <uint> [#uses=1]
369 %tmp4.mask17 = shl i32 %tmp4, i8 1 ; <uint> [#uses=1]
370 %tmp1415 = and i32 %tmp4.mask17, 2147483648 ; <uint> [#uses=1]
371 %tmp.masked = and i32 %tmp, 2147483648 ; <uint> [#uses=1]
372 %tmp11 = or i32 %tmp1415, %tmp.masked ; <uint> [#uses=1]
373 %tmp12 = and i32 %tmp9, 2147483647 ; <uint> [#uses=1]
374 %tmp13 = or i32 %tmp12, %tmp11 ; <uint> [#uses=1]
375 store i32 %tmp13, i32* %tmp8
385 rlwimi r2, r4, 0, 0, 0
389 We could collapse a bunch of those ORs and ANDs and generate the following
394 rlwinm r4, r2, 1, 0, 0
399 ===-------------------------------------------------------------------------===
401 Consider a function like this:
403 float foo(float X) { return X + 1234.4123f; }
405 The FP constant ends up in the constant pool, so we need to get the LR register.
406 This ends up producing code like this:
415 addis r2, r2, ha16(.CPI_foo_0-"L00000$pb")
416 lfs f0, lo16(.CPI_foo_0-"L00000$pb")(r2)
422 This is functional, but there is no reason to spill the LR register all the way
423 to the stack (the two marked instrs): spilling it to a GPR is quite enough.
425 Implementing this will require some codegen improvements. Nate writes:
427 "So basically what we need to support the "no stack frame save and restore" is a
428 generalization of the LR optimization to "callee-save regs".
430 Currently, we have LR marked as a callee-save reg. The register allocator sees
431 that it's callee save, and spills it directly to the stack.
433 Ideally, something like this would happen:
435 LR would be in a separate register class from the GPRs. The class of LR would be
436 marked "unspillable". When the register allocator came across an unspillable
437 reg, it would ask "what is the best class to copy this into that I *can* spill"
438 If it gets a class back, which it will in this case (the gprs), it grabs a free
439 register of that class. If it is then later necessary to spill that reg, so be
442 ===-------------------------------------------------------------------------===
446 return X ? 524288 : 0;
454 beq cr0, LBB1_2 ;entry
467 This sort of thing occurs a lot due to globalopt.
469 ===-------------------------------------------------------------------------===
473 define i32 @bar(i32 %x) nounwind readnone ssp {
475 %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1]
476 %neg = sext i1 %0 to i32 ; <i32> [#uses=1]
488 it would be better to produce:
495 ===-------------------------------------------------------------------------===
497 test/CodeGen/PowerPC/2007-03-24-cntlzd.ll compiles to:
499 __ZNK4llvm5APInt17countLeadingZerosEv:
502 or r2, r2, r2 <<-- silly.
506 The dead or is a 'truncate' from 64- to 32-bits.
508 ===-------------------------------------------------------------------------===
510 We generate horrible ppc code for this:
522 addi r5, r5, 1 ;; Extra IV for the exit value compare.
526 xoris r6, r5, 30 ;; This is due to a large immediate.
527 cmplwi cr0, r6, 33920
530 //===---------------------------------------------------------------------===//
534 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
535 { return std::make_pair(a + b, a + b < a); }
536 bool no_overflow(unsigned a, unsigned b)
537 { return !full_add(a, b).second; }
554 rlwinm r2, r2, 29, 31, 31
558 //===---------------------------------------------------------------------===//
560 We compile some FP comparisons into an mfcr with two rlwinms and an or. For
563 int test(double x, double y) { return islessequal(x, y);}
564 int test2(double x, double y) { return islessgreater(x, y);}
565 int test3(double x, double y) { return !islessequal(x, y);}
567 Compiles into (all three are similar, but the bits differ):
572 rlwinm r3, r2, 29, 31, 31
573 rlwinm r2, r2, 31, 31, 31
577 GCC compiles this into:
586 which is more efficient and can use mfocr. See PR642 for some more context.
588 //===---------------------------------------------------------------------===//
590 void foo(float *data, float d) {
592 for (i = 0; i < 8000; i++)
595 void foo2(float *data, float d) {
598 for (i = 0; i < 8000; i++) {
611 cmplwi cr0, r4, 32000
620 cmplwi cr0, r4, 32000
625 The 'mr' could be eliminated to folding the add into the cmp better.
627 //===---------------------------------------------------------------------===//
628 Codegen for the following (low-probability) case deteriorated considerably
629 when the correctness fixes for unordered comparisons went in (PR 642, 58871).
630 It should be possible to recover the code quality described in the comments.
632 ; RUN: llvm-as < %s | llc -march=ppc32 | grep or | count 3
633 ; This should produce one 'or' or 'cror' instruction per function.
635 ; RUN: llvm-as < %s | llc -march=ppc32 | grep mfcr | count 3
638 define i32 @test(double %x, double %y) nounwind {
640 %tmp3 = fcmp ole double %x, %y ; <i1> [#uses=1]
641 %tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
645 define i32 @test2(double %x, double %y) nounwind {
647 %tmp3 = fcmp one double %x, %y ; <i1> [#uses=1]
648 %tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
652 define i32 @test3(double %x, double %y) nounwind {
654 %tmp3 = fcmp ugt double %x, %y ; <i1> [#uses=1]
655 %tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
658 //===----------------------------------------------------------------------===//
659 ; RUN: llvm-as < %s | llc -march=ppc32 | not grep fneg
661 ; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and
662 ; should not be generated except with -enable-finite-only-fp-math or the like).
663 ; With the correctness fixes for PR642 (58871) LowerSELECT_CC would need to
664 ; recognize a more elaborate tree than a simple SETxx.
666 define double @test_FNEG_sel(double %A, double %B, double %C) {
667 %D = fsub double -0.000000e+00, %A ; <double> [#uses=1]
668 %Cond = fcmp ugt double %D, -0.000000e+00 ; <i1> [#uses=1]
669 %E = select i1 %Cond, double %B, double %C ; <double> [#uses=1]
673 //===----------------------------------------------------------------------===//
674 The save/restore sequence for CR in prolog/epilog is terrible:
675 - Each CR subreg is saved individually, rather than doing one save as a unit.
676 - On Darwin, the save is done after the decrement of SP, which means the offset
677 from SP of the save slot can be too big for a store instruction, which means we
678 need an additional register (currently hacked in 96015+96020; the solution there
679 is correct, but poor).
680 - On SVR4 the same thing can happen, and I don't think saving before the SP
681 decrement is safe on that target, as there is no red zone. This is currently
682 broken AFAIK, although it's not a target I can exercise.
683 The following demonstrates the problem:
684 extern void bar(char *p);
688 __asm__("" ::: "cr2");