1 //===- README.txt - Notes for improving PowerPC-specific code gen ---------===//
4 * lmw/stmw pass a la arm load store optimizer for prolog/epilog
6 ===-------------------------------------------------------------------------===
10 unsigned add32carry(unsigned sum, unsigned x) {
17 Should compile to something like:
27 rlwinm r4, r4, 29, 31, 31
32 ===-------------------------------------------------------------------------===
34 Support 'update' load/store instructions. These are cracked on the G5, but are
37 With preinc enabled, this:
39 long *%test4(long *%X, long *%dest) {
40 %Y = getelementptr long* %X, int 4
42 store long %A, long* %dest
57 with -sched=list-burr, I get:
66 ===-------------------------------------------------------------------------===
68 We compile the hottest inner loop of viterbi to:
79 bne cr0, LBB1_83 ;bb420.i
81 The CBE manages to produce:
92 This could be much better (bdnz instead of bdz) but it still beats us. If we
93 produced this with bdnz, the loop would be a single dispatch group.
95 ===-------------------------------------------------------------------------===
97 Lump the constant pool for each function into ONE pic object, and reference
98 pieces of it as offsets from the start. For functions like this (contrived
99 to have lots of constants obviously):
101 double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
106 lis r2, ha16(.CPI_X_0)
107 lfd f0, lo16(.CPI_X_0)(r2)
108 lis r2, ha16(.CPI_X_1)
109 lfd f2, lo16(.CPI_X_1)(r2)
111 lis r2, ha16(.CPI_X_2)
112 lfd f1, lo16(.CPI_X_2)(r2)
113 lis r2, ha16(.CPI_X_3)
114 lfd f2, lo16(.CPI_X_3)(r2)
118 It would be better to materialize .CPI_X into a register, then use immediates
119 off of the register to avoid the lis's. This is even more important in PIC
122 Note that this (and the static variable version) is discussed here for GCC:
123 http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
125 Here's another example (the sgn function):
126 double testf(double a) {
127 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
130 it produces a BB like this:
132 lis r2, ha16(LCPI1_0)
133 lfs f0, lo16(LCPI1_0)(r2)
134 lis r2, ha16(LCPI1_1)
135 lis r3, ha16(LCPI1_2)
136 lfs f2, lo16(LCPI1_2)(r3)
137 lfs f3, lo16(LCPI1_1)(r2)
142 ===-------------------------------------------------------------------------===
144 PIC Code Gen IPO optimization:
146 Squish small scalar globals together into a single global struct, allowing the
147 address of the struct to be CSE'd, avoiding PIC accesses (also reduces the size
148 of the GOT on targets with one).
150 Note that this is discussed here for GCC:
151 http://gcc.gnu.org/ml/gcc-patches/2006-02/msg00133.html
153 ===-------------------------------------------------------------------------===
155 No loads or stores of the constants should be needed:
157 struct foo { double X, Y; };
158 void xxx(struct foo F);
159 void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }
161 ===-------------------------------------------------------------------------===
165 We still generate calls to foo$stub, and stubs, on Darwin. This is not
166 necessary when building with the Leopard (10.5) or later linker, as stubs are
167 generated by ld when necessary. Parameterizing this based on the deployment
168 target (-mmacosx-version-min) is probably enough. x86-32 does this right, see
171 ===-------------------------------------------------------------------------===
173 Darwin Stub LICM optimization:
179 Have to go through an indirect stub if bar is external or linkonce. It would
180 be better to compile it as:
185 which only computes the address of bar once (instead of each time through the
186 stub). This is Darwin specific and would have to be done in the code generator.
187 Probably not a win on x86.
189 ===-------------------------------------------------------------------------===
191 Simple IPO for argument passing, change:
192 void foo(int X, double Y, int Z) -> void foo(int X, int Z, double Y)
194 the Darwin ABI specifies that any integer arguments in the first 32 bytes worth
195 of arguments get assigned to r3 through r10. That is, if you have a function
196 foo(int, double, int) you get r3, f1, r6, since the 64 bit double ate up the
197 argument bytes for r4 and r5. The trick then would be to shuffle the argument
198 order for functions we can internalize so that the maximum number of
199 integers/pointers get passed in regs before you see any of the fp arguments.
201 Instead of implementing this, it would actually probably be easier to just
202 implement a PPC fastcc, where we could do whatever we wanted to the CC,
203 including having this work sanely.
205 ===-------------------------------------------------------------------------===
207 Fix Darwin FP-In-Integer Registers ABI
209 Darwin passes doubles in structures in integer registers, which is very very
210 bad. Add something like a BITCAST to LLVM, then do an i-p transformation that
211 percolates these things out of functions.
213 Check out how horrible this is:
214 http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html
216 This is an extension of "interprocedural CC unmunging" that can't be done with
219 ===-------------------------------------------------------------------------===
226 return b * 3; // ignore the fact that this is always 3.
232 into something not this:
237 rlwinm r2, r2, 29, 31, 31
239 bgt cr0, LBB1_2 ; UnifiedReturnBlock
241 rlwinm r2, r2, 0, 31, 31
244 LBB1_2: ; UnifiedReturnBlock
248 In particular, the two compares (marked 1) could be shared by reversing one.
249 This could be done in the dag combiner, by swapping a BR_CC when a SETCC of the
250 same operands (but backwards) exists. In this case, this wouldn't save us
251 anything though, because the compares still wouldn't be shared.
253 ===-------------------------------------------------------------------------===
255 Fold add and sub with constant into non-extern, non-weak addresses so this:
258 void bar(int b) { a = b; }
259 void foo(unsigned char *c) {
276 lbz r2, lo16(_a+3)(r2)
280 ===-------------------------------------------------------------------------===
282 We generate really bad code for this:
284 int f(signed char *a, _Bool b, _Bool c) {
290 ===-------------------------------------------------------------------------===
293 int test(unsigned *P) { return *P >> 24; }
308 ===-------------------------------------------------------------------------===
310 On the G5, logical CR operations are more expensive in their three
311 address form: ops that read/write the same register are half as expensive as
312 those that read from two registers that are different from their destination.
314 We should model this with two separate instructions. The isel should generate
315 the "two address" form of the instructions. When the register allocator
316 detects that it needs to insert a copy due to the two-addresness of the CR
317 logical op, it will invoke PPCInstrInfo::convertToThreeAddress. At this point
318 we can convert to the "three address" instruction, to save code space.
320 This only matters when we start generating cr logical ops.
322 ===-------------------------------------------------------------------------===
324 We should compile these two functions to the same thing:
327 void f(int a, int b, int *P) {
328 *P = (a-b)>=0?(a-b):(b-a);
330 void g(int a, int b, int *P) {
334 Further, they should compile to something better than:
340 bgt cr0, LBB2_2 ; entry
357 ... which is much nicer.
359 This theoretically may help improve twolf slightly (used in dimbox.c:142?).
361 ===-------------------------------------------------------------------------===
364 define i32 @clamp0g(i32 %a) {
366 %cmp = icmp slt i32 %a, 0
367 %sel = select i1 %cmp, i32 0, i32 %a
371 Is compile to this with the PowerPC (32-bit) backend:
383 This could be reduced to the much simpler:
390 ===-------------------------------------------------------------------------===
392 int foo(int N, int ***W, int **TK, int X) {
395 for (t = 0; t < N; ++t)
396 for (i = 0; i < 4; ++i)
397 W[t / X][i][t % X] = TK[i][t];
402 We generate relatively atrocious code for this loop compared to gcc.
404 We could also strength reduce the rem and the div:
405 http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf
407 ===-------------------------------------------------------------------------===
409 float foo(float X) { return (int)(X); }
424 We could use a target dag combine to turn the lwz/extsw into an lwa when the
425 lwz has a single use. Since LWA is cracked anyway, this would be a codesize
428 ===-------------------------------------------------------------------------===
430 We generate ugly code for this:
432 void func(unsigned int *ret, float dx, float dy, float dz, float dw) {
434 if(dx < -dw) code |= 1;
435 if(dx > dw) code |= 2;
436 if(dy < -dw) code |= 4;
437 if(dy > dw) code |= 8;
438 if(dz < -dw) code |= 16;
439 if(dz > dw) code |= 32;
443 ===-------------------------------------------------------------------------===
445 %struct.B = type { i8, [3 x i8] }
447 define void @bar(%struct.B* %b) {
449 %tmp = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
450 %tmp = load i32* %tmp ; <uint> [#uses=1]
451 %tmp3 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=1]
452 %tmp4 = load i32* %tmp3 ; <uint> [#uses=1]
453 %tmp8 = bitcast %struct.B* %b to i32* ; <uint*> [#uses=2]
454 %tmp9 = load i32* %tmp8 ; <uint> [#uses=1]
455 %tmp4.mask17 = shl i32 %tmp4, i8 1 ; <uint> [#uses=1]
456 %tmp1415 = and i32 %tmp4.mask17, 2147483648 ; <uint> [#uses=1]
457 %tmp.masked = and i32 %tmp, 2147483648 ; <uint> [#uses=1]
458 %tmp11 = or i32 %tmp1415, %tmp.masked ; <uint> [#uses=1]
459 %tmp12 = and i32 %tmp9, 2147483647 ; <uint> [#uses=1]
460 %tmp13 = or i32 %tmp12, %tmp11 ; <uint> [#uses=1]
461 store i32 %tmp13, i32* %tmp8
471 rlwimi r2, r4, 0, 0, 0
475 We could collapse a bunch of those ORs and ANDs and generate the following
480 rlwinm r4, r2, 1, 0, 0
485 ===-------------------------------------------------------------------------===
487 Consider a function like this:
489 float foo(float X) { return X + 1234.4123f; }
491 The FP constant ends up in the constant pool, so we need to get the LR register.
492 This ends up producing code like this:
501 addis r2, r2, ha16(.CPI_foo_0-"L00000$pb")
502 lfs f0, lo16(.CPI_foo_0-"L00000$pb")(r2)
508 This is functional, but there is no reason to spill the LR register all the way
509 to the stack (the two marked instrs): spilling it to a GPR is quite enough.
511 Implementing this will require some codegen improvements. Nate writes:
513 "So basically what we need to support the "no stack frame save and restore" is a
514 generalization of the LR optimization to "callee-save regs".
516 Currently, we have LR marked as a callee-save reg. The register allocator sees
517 that it's callee save, and spills it directly to the stack.
519 Ideally, something like this would happen:
521 LR would be in a separate register class from the GPRs. The class of LR would be
522 marked "unspillable". When the register allocator came across an unspillable
523 reg, it would ask "what is the best class to copy this into that I *can* spill"
524 If it gets a class back, which it will in this case (the gprs), it grabs a free
525 register of that class. If it is then later necessary to spill that reg, so be
528 ===-------------------------------------------------------------------------===
532 return X ? 524288 : 0;
540 beq cr0, LBB1_2 ;entry
553 This sort of thing occurs a lot due to globalopt.
555 ===-------------------------------------------------------------------------===
559 define i32 @bar(i32 %x) nounwind readnone ssp {
561 %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1]
562 %neg = sext i1 %0 to i32 ; <i32> [#uses=1]
574 it would be better to produce:
581 ===-------------------------------------------------------------------------===
583 test/CodeGen/PowerPC/2007-03-24-cntlzd.ll compiles to:
585 __ZNK4llvm5APInt17countLeadingZerosEv:
588 or r2, r2, r2 <<-- silly.
592 The dead or is a 'truncate' from 64- to 32-bits.
594 ===-------------------------------------------------------------------------===
596 We generate horrible ppc code for this:
608 addi r5, r5, 1 ;; Extra IV for the exit value compare.
612 xoris r6, r5, 30 ;; This is due to a large immediate.
613 cmplwi cr0, r6, 33920
616 //===---------------------------------------------------------------------===//
620 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
621 { return std::make_pair(a + b, a + b < a); }
622 bool no_overflow(unsigned a, unsigned b)
623 { return !full_add(a, b).second; }
640 rlwinm r2, r2, 29, 31, 31
644 //===---------------------------------------------------------------------===//
646 We compile some FP comparisons into an mfcr with two rlwinms and an or. For
649 int test(double x, double y) { return islessequal(x, y);}
650 int test2(double x, double y) { return islessgreater(x, y);}
651 int test3(double x, double y) { return !islessequal(x, y);}
653 Compiles into (all three are similar, but the bits differ):
658 rlwinm r3, r2, 29, 31, 31
659 rlwinm r2, r2, 31, 31, 31
663 GCC compiles this into:
672 which is more efficient and can use mfocr. See PR642 for some more context.
674 //===---------------------------------------------------------------------===//
676 void foo(float *data, float d) {
678 for (i = 0; i < 8000; i++)
681 void foo2(float *data, float d) {
684 for (i = 0; i < 8000; i++) {
697 cmplwi cr0, r4, 32000
706 cmplwi cr0, r4, 32000
711 The 'mr' could be eliminated to folding the add into the cmp better.
713 //===---------------------------------------------------------------------===//
714 Codegen for the following (low-probability) case deteriorated considerably
715 when the correctness fixes for unordered comparisons went in (PR 642, 58871).
716 It should be possible to recover the code quality described in the comments.
718 ; RUN: llvm-as < %s | llc -march=ppc32 | grep or | count 3
719 ; This should produce one 'or' or 'cror' instruction per function.
721 ; RUN: llvm-as < %s | llc -march=ppc32 | grep mfcr | count 3
724 define i32 @test(double %x, double %y) nounwind {
726 %tmp3 = fcmp ole double %x, %y ; <i1> [#uses=1]
727 %tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
731 define i32 @test2(double %x, double %y) nounwind {
733 %tmp3 = fcmp one double %x, %y ; <i1> [#uses=1]
734 %tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
738 define i32 @test3(double %x, double %y) nounwind {
740 %tmp3 = fcmp ugt double %x, %y ; <i1> [#uses=1]
741 %tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
744 //===----------------------------------------------------------------------===//
745 ; RUN: llvm-as < %s | llc -march=ppc32 | not grep fneg
747 ; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and
748 ; should not be generated except with -enable-finite-only-fp-math or the like).
749 ; With the correctness fixes for PR642 (58871) LowerSELECT_CC would need to
750 ; recognize a more elaborate tree than a simple SETxx.
752 define double @test_FNEG_sel(double %A, double %B, double %C) {
753 %D = fsub double -0.000000e+00, %A ; <double> [#uses=1]
754 %Cond = fcmp ugt double %D, -0.000000e+00 ; <i1> [#uses=1]
755 %E = select i1 %Cond, double %B, double %C ; <double> [#uses=1]
759 //===----------------------------------------------------------------------===//
760 The save/restore sequence for CR in prolog/epilog is terrible:
761 - Each CR subreg is saved individually, rather than doing one save as a unit.
762 - On Darwin, the save is done after the decrement of SP, which means the offset
763 from SP of the save slot can be too big for a store instruction, which means we
764 need an additional register (currently hacked in 96015+96020; the solution there
765 is correct, but poor).
766 - On SVR4 the same thing can happen, and I don't think saving before the SP
767 decrement is safe on that target, as there is no red zone. This is currently
768 broken AFAIK, although it's not a target I can exercise.
769 The following demonstrates the problem:
770 extern void bar(char *p);
774 __asm__("" ::: "cr2");