1 //===- README_ALTIVEC.txt - Notes for improving Altivec code gen ----------===//
3 Implement TargetConstantVec, and set up PPC to custom lower ConstantVec into
4 TargetConstantVec's if it's one of the many forms that are algorithmically
5 computable using the spiffy altivec instructions.
7 //===----------------------------------------------------------------------===//
9 Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
10 registers, to generate better spill code.
12 //===----------------------------------------------------------------------===//
14 Altivec support. The first should be a single lvx from the constant pool, the
15 second should be a xor/stvx:
18 int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
24 int x[8] __attribute__((aligned(128)));
25 memset (x, 0, sizeof (x));
29 //===----------------------------------------------------------------------===//
31 Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
32 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
34 We need to codegen -0.0 vector efficiently (no constant pool load).
36 When -ffast-math is on, we can use 0.0.
38 //===----------------------------------------------------------------------===//
42 v4f32 Vector2 = { Vector.X, Vector.X, Vector.X, Vector.X };
44 Since we know that "Vector" is 16-byte aligned and we know the element offset
45 of ".X", we should change the load into a lve*x instruction, instead of doing
46 a load/store/lve*x sequence.
48 //===----------------------------------------------------------------------===//
50 There are a wide range of vector constants we can generate with combinations of
51 altivec instructions. For example, GCC does: t=vsplti*, r = t+t.
53 //===----------------------------------------------------------------------===//